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公开(公告)号：US08614919B2
公开(公告)日：2013-12-24
申请号：US13137422
申请日：2011-08-15
Applicant: Jaesoo Lee , Kangho Roh , Wonhee Cho , Hojun Shim , Youngjoon Choi , Jaehoon Heo , Je-Hyuck Song , Seung-Duk Cho , Seontaek Kim , Moonwook Oh , Jong Tae Park , Wonmoon Cheon , Chanik Park , Yang-sup Lee
Inventor： Jaesoo Lee , Kangho Roh , Wonhee Cho , Hojun Shim , Youngjoon Choi , Jaehoon Heo , Je-Hyuck Song , Seung-Duk Cho , Seontaek Kim , Moonwook Oh , Jong Tae Park , Wonmoon Cheon , Chanik Park , Yang-sup Lee
IPC: G11C16/04
CPC classification number: G11C11/5628 , G06F12/0246 , G06F2212/7201 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C16/3431 , G11C29/00 , G11C2211/5621 , Y02D10/13
Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.
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公开(公告)号：US20110302476A1
公开(公告)日：2011-12-08
申请号：US13137425
申请日：2011-08-15
Applicant: Jaesoo Lee , Kangho Roh , Wonhee Cho , Hojun Shim , Youngjoon Choi , Jaehoon Heo , Je-Hyuck Song , Seung-Duk Cho , Seontaek Kim , Moonwook Oh , Jong Tae Park , Wonmoon Cheon , Chanik Park , Yang-sup Lee
Inventor： Jaesoo Lee , Kangho Roh , Wonhee Cho , Hojun Shim , Youngjoon Choi , Jaehoon Heo , Je-Hyuck Song , Seung-Duk Cho , Seontaek Kim , Moonwook Oh , Jong Tae Park , Wonmoon Cheon , Chanik Park , Yang-sup Lee
CPC classification number: G11C11/5628 , G06F12/0246 , G06F2212/7201 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C16/3431 , G11C29/00 , G11C2211/5621 , Y02D10/13
Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.
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Patent Agency Ranking
公开(公告)号：US20110302468A1
公开(公告)日：2011-12-08
申请号：US13137424
申请日：2011-08-15
Applicant: Jaesoo Lee , Kangho Roh , Wonhee Cho , Hojun Shim , Youngjoon Choi , Jaehoon Heo , Je-Hyuck Song , Seung-Duk Cho , Seontaek Kim , Moonwook Oh , Jong Tae Park , Wonmoon Cheon , Chanik Park , Yang-sup Lee
Inventor： Jaesoo Lee , Kangho Roh , Wonhee Cho , Hojun Shim , Youngjoon Choi , Jaehoon Heo , Je-Hyuck Song , Seung-Duk Cho , Seontaek Kim , Moonwook Oh , Jong Tae Park , Wonmoon Cheon , Chanik Park , Yang-sup Lee
CPC classification number: G11C11/5628 , G06F12/0246 , G06F2212/7201 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C16/3431 , G11C29/00 , G11C2211/5621 , Y02D10/13
Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.
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14.发明申请公开(公告)号：US20110302352A1
公开(公告)日：2011-12-08
申请号：US13137423
申请日：2011-08-15
Applicant: Jaesoo Lee , Kangho Roh , Wonhee Cho , Hojun Shim , Youngjoon Choi , Jaehoon Heo , Je-Hyuck Song , Seung-Duk Cho , Seontaek Kim , Moonwook Oh , Jong Tae Park , Wonmoon Cheon , Chanik Park , Yang-sup Lee
Inventor： Jaesoo Lee , Kangho Roh , Wonhee Cho , Hojun Shim , Youngjoon Choi , Jaehoon Heo , Je-Hyuck Song , Seung-Duk Cho , Seontaek Kim , Moonwook Oh , Jong Tae Park , Wonmoon Cheon , Chanik Park , Yang-sup Lee
IPC: G06F12/02
CPC classification number: G11C11/5628 , G06F12/0246 , G06F2212/7201 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C16/3431 , G11C29/00 , G11C2211/5621 , Y02D10/13
Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.
Abstract translation: 存储器系统设置有处理器，主存储器和闪存。 通过实现加速和高数据可靠性，可以提高存储系统的性能。 存储器系统包括非易失性存储器件和被配置为驱动控制程序以控制非易失性存储器件的控制器。 即使在完成对非易失性存储器件的第一访问操作之前，控制程序也执行用于非易失性存储器件的第二访问操作。
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公开(公告)号：US20110299338A1
公开(公告)日：2011-12-08
申请号：US13137422
申请日：2011-08-15
Applicant: Jaesoo Lee , Kangho Roh , Wonhee Cho , Hojun Shim , Youngjoon Choi , Jaehoon Heo , Je-Hyuck Song , Seung-Duk Cho , Seontaek Kim , Moonwook Oh , Jong Tae Park , Wonmoon Cheon , Chanik Park , Yang-sup Lee
Inventor： Jaesoo Lee , Kangho Roh , Wonhee Cho , Hojun Shim , Youngjoon Choi , Jaehoon Heo , Je-Hyuck Song , Seung-Duk Cho , Seontaek Kim , Moonwook Oh , Jong Tae Park , Wonmoon Cheon , Chanik Park , Yang-sup Lee
IPC: G11C16/04
CPC classification number: G11C11/5628 , G06F12/0246 , G06F2212/7201 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C16/3431 , G11C29/00 , G11C2211/5621 , Y02D10/13
Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.
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16.发明申请公开(公告)号：US20100262765A1
公开(公告)日：2010-10-14
申请号：US12755644
申请日：2010-04-07
Applicant: Wonmoon CHEON , Young-Goo KO , Wonhee CHO , Yeon Ju JEONG , Donggi LEE , Hyuck-Sun KWON
Inventor： Wonmoon CHEON , Young-Goo KO , Wonhee CHO , Yeon Ju JEONG , Donggi LEE , Hyuck-Sun KWON
CPC classification number: G06F3/0644 , G06F3/0613 , G06F3/0679 , G06F12/0246 , G06F2212/7204 , G06F2212/7206
Abstract: A storage apparatus includes a memory unit and a controller to set up a memory space of the memory unit as a user data space and a spare space according to a signal representing at least one of the user data space and spare space. An electronic apparatus controls the storage apparatus, and a method controls at least one of the storage apparatus and the electronic apparatus to control a memory space of the storage apparatus.
Abstract translation: 存储装置包括存储器单元和控制器，用于根据表示用户数据空间和备用空间中的至少一个的信号，将存储器单元的存储器空间设置为用户数据空间和备用空间。 电子装置控制存储装置，并且控制存储装置和电子装置中的至少一个的方法来控制存储装置的存储空间。
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公开(公告)号：US20090228639A1
公开(公告)日：2009-09-10
申请号：US12372876
申请日：2009-02-18
Applicant: Wonhee CHO
Inventor： Wonhee CHO
CPC classification number: G06F21/79
Abstract: Disclosed is a data storage device including an external switch, a controller and a nonvolatile memory. The external switch selectively generates mode information in response to operation of the switch. The controller controls a recording operation of normal data and secured data in response to the mode information. The nonvolatile memory stores the normal data and the secured data in response to the controller.
Abstract translation: 公开了一种包括外部开关，控制器和非易失性存储器的数据存储装置。 外部开关响应于开关的操作选择性地产生模式信息。 控制器响应于模式信息控制正常数据和安全数据的记录操作。 非易失性存储器响应于控制器存储正常数据和安全数据。
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