公开(公告)号：US08671304B2

公开(公告)日：2014-03-11

申请号：US12846965

申请日：2010-07-30

Applicant: Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

Inventor： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

IPC: G06F1/04

CPC classification number: G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  G11C2207/2254

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

Abstract translation: 提供了一种方法，系统和计算机程序产品，用于基于训练信号调整存储器设备中的写时序。 例如，该方法可以包括在训练操作模式下配置存储器设备。 该方法还可以包括基于训练信号来确定数据总线上的信号和写入时钟信号之间的写时序窗口。 此外，该方法包括基于写时序窗口来调整数据总线上的信号与写入时钟信号之间的相位差。 存储器件可以基于调整后的相位差来恢复数据总线上的数据。

公开(公告)号：US08245073B2

公开(公告)日：2012-08-14

申请号：US12509409

申请日：2009-07-24

Applicant: Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

Inventor： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

IPC: G06F1/12

CPC classification number: G11C7/1045

Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

Abstract translation: 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

公开(公告)号：USD992003S1

公开(公告)日：2023-07-11

申请号：US29839182

申请日：2022-05-19

Applicant: Xiaoling Xu

Designer： Aili Yao

Abstract: FIG. 1 is a perspective view of a camera for kids, showing my new design;
FIG. 2 is another perspective view thereof;
FIG. 3 is a front view thereof;
FIG. 4 is a rear view thereof;
FIG. 5 is a left side view thereof;
FIG. 6 is a right side view thereof;
FIG. 7 is a top plan view thereof;
FIG. 8 is a bottom plan view thereof;
FIG. 9 is another front view thereof, shown in a used condition; and,
FIG. 10 is another rear view thereof, shown in a used condition.
The broken lines in the drawings are for the purpose of illustrating portions of the camera for kids that form no part of the claimed design.

公开(公告)号：US08443225B2

公开(公告)日：2013-05-14

申请号：US13584560

申请日：2012-08-13

Applicant: Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

Inventor： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

IPC: G06F1/12

CPC classification number: G11C7/1045

Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

Abstract translation: 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

公开(公告)号：US20120303995A1

公开(公告)日：2012-11-29

申请号：US13584560

申请日：2012-08-13

Applicant: Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

Inventor： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

IPC: G06F1/12 ,  G06F1/04

CPC classification number: G11C7/1045

Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

Abstract translation: 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

公开(公告)号：US20120215996A1

公开(公告)日：2012-08-23

申请号：US13462502

申请日：2012-05-02

Applicant: Xiaoling XU ,  Warren F. KRUGER

Inventor： Xiaoling XU ,  Warren F. KRUGER

IPC: G06F12/00

CPC classification number: G11C7/1006 ,  G11C7/1078 ,  G11C7/1096

Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.

Abstract translation: 在各种实施例中，通过在接口的地址线上发送数据掩码来消除专用掩码引脚。 存储器控制器从存储器客户端接收对存储器写入操作的请求，并根据客户端发送的写入数据掩码确定写入数据的粒度。 如本文所使用的，粒度表示所接收的写数据掩码的每个位适用的写数据量。 在一个实施例中，存储器控制器基于写入数据的粒度生成特定的写入命令和特定的写入数据掩码。 所生成的写入命令通常是可用的多个写入命令中最有效的，但实施例不限于此。 写命令在接口的命令行上传输，写数据掩码在接口的地址线上传输。

公开(公告)号：US20110185218A1

公开(公告)日：2011-07-28

申请号：US12846965

申请日：2010-07-30

Applicant: Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

Inventor： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

IPC: G06F1/04

CPC classification number: G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  G11C2207/2254

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

Abstract translation: 提供了一种方法，系统和计算机程序产品，用于基于训练信号调整存储器设备中的写时序。 例如，该方法可以包括在训练操作模式下配置存储器设备。 该方法还可以包括基于训练信号来确定数据总线上的信号和写入时钟信号之间的写时序窗口。 此外，该方法包括基于写时序窗口来调整数据总线上的信号与写入时钟信号之间的相位差。 存储器件可以基于调整后的相位差来恢复数据总线上的数据。

公开(公告)号：US20110019787A1

公开(公告)日：2011-01-27

申请号：US12509409

申请日：2009-07-24

Applicant: Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

Inventor： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

IPC: H04L7/00 ,  H03K19/096

CPC classification number: G11C7/1045

Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

Abstract translation: 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以便进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

公开(公告)号：US08730758B2

公开(公告)日：2014-05-20

申请号：US12490454

申请日：2009-06-24

Applicant: Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Warren Fritz Kruger ,  Xiaoling Xu ,  Toan Duc Pham ,  Aaron John Nygren

Inventor： Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Warren Fritz Kruger ,  Xiaoling Xu ,  Toan Duc Pham ,  Aaron John Nygren

IPC: G11C8/18 ,  G11C7/22 ,  G11C11/4076

CPC classification number: G11C7/22 ,  G06F13/1689 ,  G06F13/4234 ,  G11C7/222 ,  G11C11/4076

Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.

Abstract translation: 提供了一种用于调整存储器件中的写时序的方法和系统。 例如，该方法可以包括接收数据信号，写时钟信号和参考信号。 该方法还可以包括随时间检测参考信号中的相移。 参考信号的相移可用于调整数据信号和写入时钟信号之间的相位差，其中存储器件基于数据信号和写入时钟信号的调整的写入定时从数据信号中恢复数据 。

公开(公告)号：US08489912B2

公开(公告)日：2013-07-16

申请号：US12846972

申请日：2010-07-30

Applicant: Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael John Litt

Inventor： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael John Litt

IPC: G06F1/04

CPC classification number: G06F1/14 ,  G06F1/08 ,  G06F13/1689

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.

Abstract translation: 提供了一种方法，系统和计算机程序产品，用于基于命令协议来调整存储器设备中的写入定时。 例如，该方法可以包括启用写时钟数据恢复（WCDR）操作模式。 该方法还可以包括在WCDR操作模式和存储器件的另一操作模式期间将WCDR数据从处理单元发送到存储器件。 基于WCDR数据中的相移，可以调整数据总线上的信号与写入时钟信号之间的相位差。 此外，该方法可以包括基于数据总线上的信号与写入时钟信号之间调整的相位差在数据总线上传送信号。