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    Adjustment of Write Timing Based on Error Detection Techniques
    1.
    发明申请
    Adjustment of Write Timing Based on Error Detection Techniques 有权
    基于错误检测技术调整写入时序

    公开(公告)号：US20110185256A1

    公开(公告)日：2011-07-28

    申请号：US12846958

    申请日：2010-07-30

    申请人： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

    发明人： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

    IPC分类号： G06F11/08

    CPC分类号： G06F13/4243

    摘要： A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

    摘要翻译： 提供了一种方法，系统和计算机程序产品，用于基于错误检测功能的结果来调整存储器件中的写入定时。 例如，该方法可以包括基于错误检测功能的结果来确定数据总线上的信号与写入时钟信号之间的写时序窗口。 该方法还可以包括基于写时序窗口来调整数据总线上的信号与写入时钟信号之间的相位差。 存储器件可以基于调整后的相位差来恢复数据总线上的数据。

    Adjustment of write timing based on error detection techniques
    4.
    发明授权
    Adjustment of write timing based on error detection techniques 有权
    基于错误检测技术调整写时序

    公开(公告)号：US08862966B2

    公开(公告)日：2014-10-14

    申请号：US12846958

    申请日：2010-07-30

    申请人： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

    发明人： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

    IPC分类号： H03M13/00 ,  G06F13/42

    CPC分类号： G06F13/4243

    摘要： A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

    摘要翻译： 提供了一种方法，系统和计算机程序产品，用于基于错误检测功能的结果来调整存储器件中的写入定时。 例如，该方法可以包括基于错误检测功能的结果来确定数据总线上的信号与写入时钟信号之间的写时序窗口。 该方法还可以包括基于写时序窗口调整数据总线上的信号与写时钟信号之间的相位差。 存储器件可以基于调整后的相位差来恢复数据总线上的数据。

    Command protocol for adjustment of write timing delay
    6.
    发明授权
    Command protocol for adjustment of write timing delay 有权
    用于调整写时序延迟的命令协议

    公开(公告)号：US08489912B2

    公开(公告)日：2013-07-16

    申请号：US12846972

    申请日：2010-07-30

    申请人： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael John Litt

    发明人： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael John Litt

    IPC分类号： G06F1/04

    CPC分类号： G06F1/14 ,  G06F1/08 ,  G06F13/1689

    摘要： A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.

    摘要翻译： 提供了一种方法，系统和计算机程序产品，用于基于命令协议来调整存储器设备中的写入定时。 例如，该方法可以包括启用写时钟数据恢复（WCDR）操作模式。 该方法还可以包括在WCDR操作模式和存储器件的另一操作模式期间将WCDR数据从处理单元发送到存储器件。 基于WCDR数据中的相移，可以调整数据总线上的信号与写入时钟信号之间的相位差。 此外，该方法可以包括基于数据总线上的信号与写入时钟信号之间调整的相位差在数据总线上传送信号。

    Command Protocol for Adjustment of Write Timing Delay
    7.
    发明申请
    Command Protocol for Adjustment of Write Timing Delay 有权
    用于调整写时序延迟的命令协议

    公开(公告)号：US20110208989A1

    公开(公告)日：2011-08-25

    申请号：US12846972

    申请日：2010-07-30

    申请人： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael John Litt

    发明人： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael John Litt

    IPC分类号： G06F1/08

    CPC分类号： G06F1/14 ,  G06F1/08 ,  G06F13/1689

    摘要： A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.

    摘要翻译： 提供了一种方法，系统和计算机程序产品，用于基于命令协议来调整存储器设备中的写入定时。 例如，该方法可以包括启用写时钟数据恢复（WCDR）操作模式。 该方法还可以包括在WCDR操作模式和存储器件的另一操作模式期间将WCDR数据从处理单元发送到存储器件。 基于WCDR数据中的相移，可以调整数据总线上的信号与写入时钟信号之间的相位差。 此外，该方法可以包括基于数据总线上的信号与写入时钟信号之间调整的相位差在数据总线上传送信号。

    Method and apparatus synchronizing integrated circuit clocks
    9.
    发明授权
    Method and apparatus synchronizing integrated circuit clocks 有权
    方法和装置同步集成电路时钟

    公开(公告)号：US08245073B2

    公开(公告)日：2012-08-14

    申请号：US12509409

    申请日：2009-07-24

    申请人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    发明人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    IPC分类号： G06F1/12

    CPC分类号： G11C7/1045

    摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

    摘要翻译： 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

    Method and apparatus synchronizing integrated circuit clocks
    10.
    发明授权
    Method and apparatus synchronizing integrated circuit clocks 有权
    方法和装置同步集成电路时钟

    公开(公告)号：US08443225B2

    公开(公告)日：2013-05-14

    申请号：US13584560

    申请日：2012-08-13

    申请人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    发明人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    IPC分类号： G06F1/12

    CPC分类号： G11C7/1045

    摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

    摘要翻译： 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。