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    Method and apparatus synchronizing integrated circuit clocks
    1.
    发明授权
    Method and apparatus synchronizing integrated circuit clocks 有权
    方法和装置同步集成电路时钟

    公开(公告)号：US08245073B2

    公开(公告)日：2012-08-14

    申请号：US12509409

    申请日：2009-07-24

    申请人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    发明人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    IPC分类号： G06F1/12

    CPC分类号： G11C7/1045

    摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

    摘要翻译： 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

    Method and apparatus synchronizing integrated circuit clocks
    2.
    发明授权
    Method and apparatus synchronizing integrated circuit clocks 有权
    方法和装置同步集成电路时钟

    公开(公告)号：US08443225B2

    公开(公告)日：2013-05-14

    申请号：US13584560

    申请日：2012-08-13

    申请人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    发明人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    IPC分类号： G06F1/12

    CPC分类号： G11C7/1045

    摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

    摘要翻译： 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

    METHOD AND APPARATUS SYNCHRONIZING INTEGRATED CIRCUIT CLOCKS
    3.
    发明申请
    METHOD AND APPARATUS SYNCHRONIZING INTEGRATED CIRCUIT CLOCKS 有权
    方法和装置同步集成电路时钟

    公开(公告)号：US20120303995A1

    公开(公告)日：2012-11-29

    申请号：US13584560

    申请日：2012-08-13

    申请人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    发明人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    IPC分类号： G06F1/12 ,  G06F1/04

    CPC分类号： G11C7/1045

    摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

    摘要翻译： 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

    Method and Apparatus Synchronizing Integrated Circuit Clocks
    4.
    发明申请
    Method and Apparatus Synchronizing Integrated Circuit Clocks 有权
    同步集成电路时钟的方法和装置

    公开(公告)号：US20110019787A1

    公开(公告)日：2011-01-27

    申请号：US12509409

    申请日：2009-07-24

    申请人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    发明人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    IPC分类号： H04L7/00 ,  H03K19/096

    CPC分类号： G11C7/1045

    摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

    摘要翻译： 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以便进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

    Unified Data Masking, Data Poisoning, and Data Bus Inversion Signaling
    6.
    发明申请
    Unified Data Masking, Data Poisoning, and Data Bus Inversion Signaling 有权
    统一数据屏蔽，数据中断和数据总线反向信令

    公开(公告)号：US20130159818A1

    公开(公告)日：2013-06-20

    申请号：US13325648

    申请日：2011-12-14

    申请人： James O'Connor ,  Aaron Nygren ,  Anwar Kashem ,  Warren Fritz Kruger ,  Bryan Black

    发明人： James O'Connor ,  Aaron Nygren ,  Anwar Kashem ,  Warren Fritz Kruger ,  Bryan Black

    IPC分类号： G06F11/07

    CPC分类号： G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

    摘要： Provided herein is a method and system for providing and analyzing unified data signaling that includes setting, or analyzing a state of a single indicator signal, generating or analyzing a data pattern of a plurality of data bits, and signal, or determine, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned.

    摘要翻译： 本文提供了一种用于提供和分析统一数据信令的方法和系统，其包括设置或分析单个指示符信号的状态，生成或分析多个数据位的数据模式，以及基于 单个指示符信号的状态和多个数据位的模式，数据总线反转已被应用于多个数据位或多个数据位被中毒。

    Interconnect Redundancy for Multi-Interconnect Device
    7.
    发明申请
    Interconnect Redundancy for Multi-Interconnect Device 审中-公开
    多互连设备的互连冗余

    公开(公告)号：US20130159587A1

    公开(公告)日：2013-06-20

    申请号：US13326663

    申请日：2011-12-15

    申请人： Aaron Nygren ,  Anwar Kashem ,  Bryan Black ,  James Michael O'Connor ,  Warren F. Kruger

    发明人： Aaron Nygren ,  Anwar Kashem ,  Bryan Black ,  James Michael O'Connor ,  Warren F. Kruger

    IPC分类号： G06F13/36

    CPC分类号： G11C29/702 ,  G11C5/063

    摘要： A multi-interconnect integrated circuit device includes an input/output (I/O) circuit for conveying a plurality of interleaved data channel groups by configuring the I/O circuit to convey a first data channel group over a default fixed interconnect signal paths if there are no connection failures in the default fixed interconnect signal paths, and to convey the first data channel group over a second plurality of default fixed interconnect signal paths if there is at least one connection failure in the first plurality of default fixed interconnect signal paths, where the second plurality of default fixed interconnect signal paths includes a redundant fixed interconnect signal path for replacing a failed interconnect signal path from the first plurality of default fixed interconnect signal paths.

    摘要翻译： 多互连集成电路装置包括用于通过配置I / O电路来输送多个交错数据信道组的输入/输出（I / O）电路，以在默认的固定互连信号路径上传送第一数据信道组，如果 在默认固定互连信号路径中没有连接故障，并且如果在第一多个默认固定互连信号路径中存在至少一个连接故障，并且在第二多个默认固定互连信号路径上传送第一数据信道组，其中 所述第二多个默认固定互连信号路径包括用于从所述第一多个默认固定互连信号路径替换故障互连信号路径的冗余固定互连信号路径。

    Circuits and methods for error coding data blocks
    8.
    发明授权
    Circuits and methods for error coding data blocks 有权
    用于错误编码数据块的电路和方法

    公开(公告)号：US08161344B2

    公开(公告)日：2012-04-17

    申请号：US12046099

    申请日：2008-03-11

    申请人： Aaron Nygren

    发明人： Aaron Nygren

    IPC分类号： H03M13/00

    CPC分类号： G11C7/1006 ,  G06F11/1004 ,  G11C7/24 ,  G11C2029/0411

    摘要： A description is given of a circuit for creating an error coding data block for a first data block, including a first error coding path adapted to create the error coding data block in accordance with a first error coding; and a second error coding path adapted to create the error coding data block in accordance with a second error coding; the error coding data block for the first data block being created optionally by the first or second error coding paths, as a function of a control indicator, and at least the first error coding path comprising a data arrangement alteration device.

    摘要翻译： 给出了用于创建用于第一数据块的错误编码数据块的电路的描述，包括根据第一错误编码创建错误编码数据块的第一错误编码路径; 以及第二错误编码路径，其适于根据第二错误编码创建所述错误编码数据块; 由第一或第二错误编码路径可选地由第一或第二错误编码路径创建的第一数据块的错误编码数据块作为控制指示符的函数，并且至少包括数据排列改变装置的第一错误编码路径。

    Pseudodynamic off-chip driver calibration
    9.
    发明授权
    Pseudodynamic off-chip driver calibration 有权
    伪动态片外驱动器校准

    公开(公告)号：US07304495B2

    公开(公告)日：2007-12-04

    申请号：US10975384

    申请日：2004-10-29

    申请人： Aaron Nygren

    发明人： Aaron Nygren

    IPC分类号： H03K17/16

    CPC分类号： H03K19/0005

    摘要： A driver system, a driver calibration circuit arrangement for calibration of an impedance of a driver circuit arrangement, and a method for calibration of an impedance of a driver circuit arrangement can achieve improved driver behavior, with respect to undesirable distortions of the slew rate caused by off-chip drivers of DDR memory modules. A driver system has a first driver part with at least one variable impedance by which an operating point of the first driver part is determined with respect to a first potential and a second potential. The potentials supply the first driver part. A first monitoring device adjusts an impedance value of the variable impedance such that the operating point differs from a mid-point of the first and of the second potential.

    摘要翻译： 用于校准驱动器电路装置的阻抗的驱动器系统，驱动器校准电路装置以及用于校准驱动器电路装置的阻抗的方法可以相对于由不正确的由 DDR内存模块的片外驱动程序。 驱动器系统具有至少一个可变阻抗的第一驱动器部分，通过该第一驱动器部分确定第一驱动器部分的工作点相对于第一电位和第二电位。 潜力提供了第一个司机部分。 第一监视装置调整可变阻抗的阻抗值，使得工作点与第一和第二电位的中点不同。