公开(公告)号：US12190994B2

公开(公告)日：2025-01-07

申请号：US18090574

申请日：2022-12-29

Applicant: XILINX, INC.

Inventor： Kumar Rahul ,  Santosh Yachareni ,  Mahendrakumar Gunasekaran ,  Mohammad Anees

IPC: G11C7/22 ,  G11C7/10

Abstract: An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generates a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry. The self-time path circuitry of a memory receives the clock signal and generates a reset signal based on the clock signal. The plurality of driver circuitry outputs and the clock signal are based on the reset signal, and the self-time path circuitry corresponds to one or more columns of a memory bank.

公开(公告)号：US12190077B2

公开(公告)日：2025-01-07

申请号：US17993464

申请日：2022-11-23

Applicant: XILINX, INC.

Inventor： Sai Ram Venkata Pattabhi Nedunuri ,  Killivalavan Kaliyamoorthy

IPC: G06F5/06 ,  G06F1/10 ,  H04L25/02

Abstract: A communication system includes link circuits that receive serial data over one or more input serial links. The link circuits include a primary link circuit and a secondary link circuit. The secondary link circuit includes a de-serializer circuit configured to receive the serial data from the one or more input serial links and convert the serial data into parallel data, and an aligner circuit comprising a memory. The aligner circuit stops at least one of storing the parallel data in the memory and reading the memory based on a channel bonding signal generated based on a channel bonding symbol within the serial data. The aligner circuit outputs the channel bonding signal to a finite state machine (FSM) circuit of the primary link circuit. The aligner circuit outputs the parallel data based on receiving a read signal from the FSM circuit of the primary link circuit.

公开(公告)号：US20250006694A1

公开(公告)日：2025-01-02

申请号：US18215685

申请日：2023-06-28

Applicant: XILINX, INC.

Inventor： Martin L. VOOGEL ,  Matthew H. KLEIN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

Abstract: Examples herein describe techniques for producing a three-dimensional (3D) die stack. The techniques include stacking a first die on top of a second die. The first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die. The techniques further include stacking a third die on top of the second die. The third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die.

公开(公告)号：US20240429145A1

公开(公告)日：2024-12-26

申请号：US18214381

申请日：2023-06-26

Applicant: XILINX, INC.

Inventor： Praful JAIN ,  Brian C. GAIDE ,  Martin L. VOOGEL

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments herein describe techniques to build multi-die field-programmable gate arrays (FPGAs) using chip-on-wafer (CoW) technology. In an embodiment, FPGA chiplets (i.e., dies) and an interposer substrate include respective hybrid bonding connectors. Metal layers of the interposer substrate are patterned to provide inter-die communications amongst the multiple dies via the hybrid bonding connectors, and the dies communicate with one another via the hybrid bonding connectors using a non-serialized protocol native to the FPGA. The dies may communicate with one another through edge-based hybrid bonding connectors (e.g., in a symmetrical fashion). The metal layers of the interposer substrate may also support intra-die communications (e.g., data, clocks, and/or controls) and/or provide power, clock(s), and/or configuration parameters to the dies via hybrid bonding connectors within central regions of the dies. The IC device may include more than 1000 tracks per millimeter (e.g., more than 1600, 2800, 3500, or greater).

公开(公告)号：US20240419626A1

公开(公告)日：2024-12-19

申请号：US18336777

申请日：2023-06-16

Applicant: Xilinx, Inc.

Inventor： Paul Robert Schumacher ,  Anurag Dubey

IPC: G06F15/78

Abstract: Performance evaluation of a heterogeneous hardware platform includes implementing a traffic generator design in an integrated circuit. The traffic generator design includes traffic generator kernels including a traffic generator kernel implemented in a data processing array of the integrated circuit and a traffic generator kernel implemented in a programmable logic of the integrated circuit. The traffic generator design is executed in the integrated circuit. The traffic generator kernels implement data access patterns by, at least in part, generating dummy data. Performance data is generated from executing the traffic generator design in the integrated circuit. The performance data is output from the integrated circuit.

公开(公告)号：US20240411967A1

公开(公告)日：2024-12-12

申请号：US18333372

申请日：2023-06-12

Applicant: Xilinx, Inc.

Inventor： Lin-Ya Yu ,  Alexandre Isoard ,  Hem C. Neema

IPC: G06F30/323

Abstract: High-level synthesis of designs using loop-aware execution information includes generating, using computer hardware, an intermediate representation (IR) of a design specified in a high-level programming language. The design is for an integrated circuit. Execution information analysis is performed on the IR of the design generating analysis results for functions of the design. The analysis results of the design are transformed by embedding the analysis results in a plurality of regions of the IR of the design. Selected regions of the plurality of regions are merged based on the analysis results, as embedded, for the selected regions. The IR of the design is scheduled using the analysis results subsequent to the merging.

公开(公告)号：US12160256B2

公开(公告)日：2024-12-03

申请号：US17559592

申请日：2021-12-22

Applicant: XILINX, INC.

Inventor： Chi Fung Poon ,  Chuen-Huei Chou ,  Weerachai Neeranartvong ,  Kevin Zheng

IPC: H04B1/04 ,  H03M1/66 ,  H03M1/74

Abstract: A DAC-based transmit driver architecture with improved bandwidth and techniques for driving data using such an architecture. One example transmit driver circuit generally includes an output node and a plurality of digital-to-analog converter (DAC) slices. Each DAC slice has an output coupled to the output node of the transmit driver circuit and includes a bias transistor having a drain coupled to the output of the DAC slice and a multiplexer having a plurality of inputs and an output coupled to a source of the bias transistor.

公开(公告)号：US20240396638A1

公开(公告)日：2024-11-28

申请号：US18202512

申请日：2023-05-26

Applicant: XILINX, INC.

Inventor： Adebabay M. BEKELE ,  Mayank RAJ ,  Chuan XIE ,  Sandeep KUMAR ,  Zhaowen WANG ,  Sukruth PATTANAGIRI GIRIYAPPA ,  Parag UPADHYAYA ,  Yohan FRANS

IPC: H04B10/54 ,  H04B10/50 ,  H04B10/508

Abstract: Some examples described herein provide for controlling output modulation amplitude for optoelectronic devices. In an example, a method includes transmitting a first data pattern to an optical modulator device. The method also includes determining, while transmitting the first data pattern and for each heater control value of a plurality of heater control values for a heater, a photodiode current value associated with the optical modulator device to generate a plurality of photodiode current values corresponding to the plurality of heater control values. The method also includes determining a maximum optical modulation amplitude for the optical modulator device based at least in part on the plurality of photodiode current values corresponding to the plurality of heater control values. The method also includes controlling the heater for the optical modulator device based on the maximum optical modulation amplitude.

公开(公告)号：US20240396550A1

公开(公告)日：2024-11-28

申请号：US18200432

申请日：2023-05-22

Applicant: XILINX, INC.

Inventor： Wenyi SONG ,  Shadi BARAKAT

IPC: H03K19/003 ,  G11C11/408 ,  H03K3/037 ,  H03K19/0185

Abstract: Driver circuitry for memory controller circuitry includes level shifter circuitry, inverter circuitry, and output circuitry. The level shifter circuitry receives an input data signal and outputs a first level shifted data signal and a second level shifted data signal based on the input data signal. The inverter circuitry is connected to the level shifter circuitry, receives the first level shifted data signal and the second level shifted data signal, and outputs a first inverted data signal via a first output node and a second inverted data signal via a second output node. The inverter circuitry includes mitigation circuitry coupled to the first output node and the second output node and alters one or more of the first inverted data signal and the second inverted data signal. The output circuitry outputs an output data signal based on the first inverted data signal and the second inverted data signal.

公开(公告)号：US12147379B2

公开(公告)日：2024-11-19

申请号：US18089780

申请日：2022-12-28

Applicant: XILINX, INC.

Inventor： Rajeev Patwari ,  Jorn Tuyls ,  Elliott Delaye ,  Xiao Teng ,  Ephrem Wu

IPC: G06F15/78 ,  G06F13/28

Abstract: Examples herein describe techniques for performing parallel processing using a plurality of processing elements (PEs) and a controller for data that has data dependencies. For example, a calculation may require an entire row or column to be summed, or to determine its mean. The PEs can be assigned different chunks of a data set (e.g., a tensor set, a column, or a row) for processing. The PEs can use one or more tokens to inform the controller when they are done with partial processing of their data chunks. The controller can then gather the partial results and determine an intermediate value for the data set. The controller can then distribute this intermediate value to the PEs which then re-process their respective data chunks using the intermediate value to generate final results.