Mouse CIA protein and CIA gene having anti-apoptotic activity as a selective inhibitor of CAD interacting ASK1 use thereof
    11.
    发明授权
    Mouse CIA protein and CIA gene having anti-apoptotic activity as a selective inhibitor of CAD interacting ASK1 use thereof 有权
    具有抗凋亡活性的小鼠CIA蛋白和CIA基因作为CAD的选择性抑制剂相互作用ASK1的用途

    公开(公告)号:US06987089B1

    公开(公告)日:2006-01-17

    申请号:US10296655

    申请日:2000-06-26

    CPC classification number: C07K14/4703 A61K38/00 C07K14/4747

    Abstract: The present invention relates to novel mouse CIA protein and CIA gene having anti-apoptotic activity isolated by yeast 2-hybrid screening which inhibit apoptosis mediated by caspase activated-DNase, CAD and apoptosis signal-regulating kinase 1, ASK1. Since mouse CIA protein and CIA gene of the present invention inhibit apoptotic cell death and DNA fragmentation by selectively interacting with CAD and ASK1 as a negative regulator, CIA protein is useful for an effective inhibitor of CAD and ASK1 protein or a cure of various diseases related to cell death such as disease of degenerative cranial nerve system, apoplexy, cancer, immune disorders or inflammation, and CIA gene is effective for a gene theraphy of the same diseases.

    Abstract translation: 本发明涉及通过酵母双杂交筛选分离的具有抗凋亡活性的小鼠CIA蛋白和CIA基因,其抑制胱天蛋白酶激活的DNA酶,CAD和凋亡信号调节激酶1(ASK1)介导的凋亡。 由于本发明的小鼠CIA蛋白和CIA基因通过与CAD和ASK1作为阴性调节剂选择性相互作用而抑制凋亡性细胞死亡和DNA片段化,CIA蛋白可用于有效的CAD和ASK1蛋白抑制剂或治愈各种疾病相关 细胞死亡如退行性脑神经系统疾病,中风,癌症,免疫疾病或炎症,以及CIA基因对于相同疾病的基因治疗是有效的。

    Analog front end circuit and method of compensating for DC offset in the analog front end circuit
    12.
    发明授权
    Analog front end circuit and method of compensating for DC offset in the analog front end circuit 失效
    模拟前端电路和模拟前端电路补偿直流偏移的方法

    公开(公告)号:US06985098B2

    公开(公告)日:2006-01-10

    申请号:US10844750

    申请日:2004-05-13

    Applicant: Yong-Hee Lee

    Inventor: Yong-Hee Lee

    CPC classification number: H03F1/304 H03F2200/375 H03M1/1019 H03M1/12

    Abstract: DC offset is compensated for in an analog front end (AFE) circuit having an amplifier and an analog-to-digital converter (ADC). First data processed by the ADC are low pass filtered and estimated DC offset data of the ADC are obtained in ADC DC offset calibration mode. Second data processed by the ADC and the amplifier are low pass filtered, and a first DC offset of the ADC are substantially removed from the filtered second data by subtracting the estimated DC offset data from the filtered second data, thereby obtaining second compensated DC offset data of the amplifier in an amplifier DC offset calibration mode. The second compensated DC offset data is iteratively improved and first compensated DC offset data of the amplifier are obtained. The first compensated DC offset data are transformed into an analog signal, and the analog signal is subtracted from an input signal of the amplifier during operation mode.

    Abstract translation: 在具有放大器和模数转换器(ADC)的模拟前端(AFE)电路中补偿DC偏移。 由ADC处理的第一个数据是低通滤波的,ADC的ADC偏移校准模式获得ADC的估计直流偏移数据。 由ADC和放大器处理的第二数据被低通滤波,并且通过从经滤波的第二数据中减去估计的DC偏移数据,从滤波后的第二数据基本上去除了ADC的第一DC偏移,从而获得第二补偿的DC偏移数据 的放大器在DC偏移校准模式下。 迭代地改善第二补偿DC偏移数据,并且获得放大器的第一补偿DC偏移数据。 将第一补偿DC偏移数据变换为模拟信号,并且在运行模式期间从放大器的输入信号中减去模拟信号。

    Negative self-bias circuit for FET mixers
    15.
    发明授权
    Negative self-bias circuit for FET mixers 失效
    用于FET混频器的负自偏置电路

    公开(公告)号:US6163689A

    公开(公告)日:2000-12-19

    申请号:US941476

    申请日:1997-09-30

    Applicant: Yong Hee Lee

    Inventor: Yong Hee Lee

    CPC classification number: H03D7/125

    Abstract: An improved mixing circuit includes a MESFET having an LO signal coupled to its gate through a charging capacitor and an RF signal coupled to its drain through a first bandpass filter. Electrons are pumped onto the charging capacitor to bias the gate of the MESFET. The MESFET drain is coupled to a second bandpass filter which passes a signal at the mixed frequency.

    Abstract translation: 改进的混合电路包括具有通过充电电容器耦合到其栅极的LO信号的MESFET和通过第一带通滤波器耦合到其漏极的RF信号。 电子被泵送到充电电容器上以偏置MESFET的栅极。 MESFET漏极耦合到通过混合频率信号的第二带通滤波器。

    Multi-channel audio signal converting device using time-varying digital filter, electronic system including the same, and method of converting multi-channel audio signal
    16.
    发明授权
    Multi-channel audio signal converting device using time-varying digital filter, electronic system including the same, and method of converting multi-channel audio signal 有权
    使用时变数字滤波器的多声道音频信号转换装置,包括其的电子系统以及多声道音频信号的转换方法

    公开(公告)号:US09311957B2

    公开(公告)日:2016-04-12

    申请号:US13755225

    申请日:2013-01-31

    CPC classification number: G11B20/10037 H04N5/04 H04N5/607

    Abstract: A multi-channel audio signal converting device using a time-varying digital filter, an electronic system including the same, and a method of converting an audio signal using the time-varying digital filter are provided. The multi-channel audio signal converting device includes a first signal channel and a second signal channel configured to perform analog-to-digital conversion or digital-to-analog conversion using a first clock signal; and a first time-varying filter configured to synchronize a digital audio signal synchronized with a second clock signal different from the first clock signal with the first clock signal and to input the digital audio signal to the second signal channel when digital-to-analog conversion is performed or to synchronize an output signal of the second signal channel with the second clock signal when analog-to-digital conversion is performed.

    Abstract translation: 提供了使用时变数字滤波器的多声道音频信号转换装置,包括该多声道数字滤波器的电子系统以及使用时变数字滤波器来转换音频信号的方法。 多声道音频信号转换装置包括第一信号通道和第二信号通道,其被配置为使用第一时钟信号执行模数转换或数模转换; 以及第一时变滤波器,被配置为使与第一时钟信号不同于第一时钟信号的第二时钟信号同步的数字音频信号与第一时钟信号同步,并且当数模转换时将数字音频信号输入到第二信号通道 或者当执行模数转换时,使第二信号通道的输出信号与第二时钟信号同步。

    Housing structure for a slide type mobile communication terminal
    17.
    发明授权
    Housing structure for a slide type mobile communication terminal 有权
    滑动式移动通信终端的外壳结构

    公开(公告)号:US08600448B2

    公开(公告)日:2013-12-03

    申请号:US12797569

    申请日:2010-06-09

    CPC classification number: H04M1/0237

    Abstract: A mobile terminal includes a front body, a rear body, and a slide module connecting the front body to the rear body such that the front body is slidable with respect to the rear body, the slide module including a first slide member fixed to a front surface of the rear body and having a rail unit at both sides of the rear body, the rail unit having a specific length corresponding to a slide stroke of the front body; and a second slide member fixed to a rear surface of the front body and having a moving guide constrained to the rail unit at both sides of the rear body and slidably moved along the rail unit, in which the moving guide protrudes toward the rear body in order to receive the rail unit and cover the rail unit.

    Abstract translation: 移动终端包括前身体,后身体和滑动模块,其将前身体连接到后身体,使得前身体相对于后身体可滑动,滑动模块包括固定到前部的第一滑动构件 后体的表面,并且在后体的两侧具有轨道单元,轨道单元具有对应于前身体的滑动行程的特定长度; 以及第二滑动构件,其固定到所述前体的后表面,并且具有被限制在所述后体的两侧处的所述轨道单元并且沿着所述轨道单元滑动地移动的移动引导件,所述移动引导件在所述轨道单元中朝向所述后体突出 接收轨道单元并覆盖轨道单元。

    Black organic light-emitting diode device
    18.
    发明授权
    Black organic light-emitting diode device 有权
    黑色有机发光二极管装置

    公开(公告)号:US08536781B2

    公开(公告)日:2013-09-17

    申请号:US13465121

    申请日:2012-05-07

    CPC classification number: H01L51/5281

    Abstract: The present invention relates to a black organic light-emitting diode that implements a resonant absorbing configuration, the black organic light-emitting diode comprising: a glass substrate; a first metal layer formed on the glass substrate; a first electrode formed on the first metal layer; an organic light-emitting layer formed on the first electrode; a second electrode formed on the organic light-emitting layer, opposite the first electrode; a first interlayer formed on the second electrode; a second metal layer formed on the first interlayer; and a second interlayer formed on the second metal layer, wherein by controlling the thickness of the first interlayer and the second interlayer, external light reflected by the first metal layer and the second electrode destructively interferes with light reflected by the second metal layer.

    Abstract translation: 本发明涉及一种实现谐振吸收结构的黑色有机发光二极管,该黑色有机发光二极管包括:玻璃基板; 形成在所述玻璃基板上的第一金属层; 形成在所述第一金属层上的第一电极; 形成在所述第一电极上的有机发光层; 形成在所述有机发光层上的与所述第一电极相对的第二电极; 形成在第二电极上的第一中间层; 形成在所述第一中间层上的第二金属层; 以及形成在所述第二金属层上的第二中间层,其中通过控制所述第一中间层和所述第二中间层的厚度,由所述第一金属层和所述第二电极反射的外部光破坏地干扰由所述第二金属层反射的光。

    Phase-locked loop lock detect
    19.
    发明授权
    Phase-locked loop lock detect 有权
    锁相环锁定检测

    公开(公告)号:US08456206B2

    公开(公告)日:2013-06-04

    申请号:US13164098

    申请日:2011-06-20

    CPC classification number: H03L7/095 H03L7/18

    Abstract: Apparatus and methods for detecting a lock in a phase-locked loop (PLL) are disclosed. In one aspect, a lock detect component includes a reference multiplier and a lock detect. The reference multiplier can receive a reference signal, a divider signal, and a voltage-controlled oscillator (VCO) output generated by a VCO in a PLL from which the divider signal is generated. The reference multiplier can also generate a multiplied reference signal using the reference signal and the VCO output. The multiplied reference signal can have a frequency that is an integer multiple of a frequency of the reference signal. The lock detect can detect a phase lock of the reference signal and the divider signal based at least in part on comparing a signal generated from a delayed reference signal and a signal generated from a delayed divider signal for a predetermined period of time.

    Abstract translation: 公开了一种用于检测锁相环(PLL)锁定的装置和方法。 一方面,锁定检测部件包括参考乘法器和锁定检测。 参考乘法器可以接收由PLL产生的VCO产生的分频器信号,分频器信号和由VCO产生的压控振荡器(VCO)输出。 参考乘法器还可以使用参考信号和VCO输出产生相乘的参考信号。 倍增的参考信号可以具有作为参考信号的频率的整数倍的频率。 锁定检测可以至少部分地基于将从延迟的参考信号产生的信号与从延迟的分频器信号产生的信号相比较预定的时间段来检测参考信号和分频器信号的锁相。

    Half-bridge three-level PWM amplifier and audio processing apparatus including the same
    20.
    发明授权
    Half-bridge three-level PWM amplifier and audio processing apparatus including the same 有权
    半桥三电平PWM放大器和音频处理装置包括相同

    公开(公告)号:US08362832B2

    公开(公告)日:2013-01-29

    申请号:US12850782

    申请日:2010-08-05

    CPC classification number: H03F3/2173 H03G3/007

    Abstract: A half-bridge three-level pulse width modulation (PWM) amplifier includes a prescaling unit, a PWM generator configured to convert the input signal to a three-level PWM signal having a first level, a second level and a reference level and an output stage. The prescaling unit scales an input signal according to at least one gain value to provide a scaled signal. The PWM generator varies the width of pulses having the first level and varies the width of pulses having a second level based on the scaled signal. The output stage drives an output node to a level of a first power supply voltage, a second power supply voltage or a third power supply voltage based on the three-level PWM signal. The output node is connected to a load. The magnitude of the at least one gain value compensates for variations of power supply voltages.

    Abstract translation: 半桥三电平脉宽调制(PWM)放大器包括一个预分频单元,一个PWM发生器,被配置为将输入信号转换成具有第一电平,第二电平和参考电平的三电平PWM信号,以及输出 阶段。 预分频单元根据至少一个增益值缩放输入信号以提供缩放信号。 PWM发生器改变具有第一电平的脉冲的宽度,并且基于缩放的信号改变具有第二电平的脉冲的宽度。 输出级基于三电平PWM信号将输出节点驱动到第一电源电压,第二电源电压或第三电源电压的电平。 输出节点连接到一个负载。 至少一个增益值的大小补偿电源电压的变化。

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