公开(公告)号：US07173841B2

公开(公告)日：2007-02-06

申请号：US10904897

申请日：2004-12-03

Applicant: Yuan-Ching Peng ,  Shyue-Shyn Lin ,  Wei-Ming Chen

Inventor： Yuan-Ching Peng ,  Shyue-Shyn Lin ,  Wei-Ming Chen

IPC: G11C5/08

CPC classification number: G11C11/15 ,  G11C5/063

Abstract: A magnetic random access memory (MRAM) device disclosed herein includes an array of magnetic memory cells having magnetoresistive (MR) stacks. The MRAM array also includes a series of bit lines and word lines coupled to the MR stacks. The array layout provides for reduced crosstalk between neighboring memory cells by increasing a distance between neighboring MR stacks along a common conductor without increasing the overall layout area of the MRAM array. Several embodiments are disclosed where neighboring MR stacks are offset such that the MR stacks are staggered. For example, groups of MR stacks coupled to a common word line or to a common bit line can be staggered. The staggered layout provides for increased distance between neighboring MR stacks for a given MRAM array area, thereby resulting in a reduction of crosstalk, for example during write operations.

Abstract translation: 本文公开的磁性随机存取存储器（MRAM）装置包括具有磁阻（MR）堆叠的磁存储器单元阵列。 MRAM阵列还包括耦合到MR堆叠的一系列位线和字线。 阵列布局通过增加沿着公共导体的相邻MR堆叠之间的距离而不增加MRAM阵列的总体布局面积来提供相邻存储器单元之间减少的串扰。 公开了几个实施例，其中相邻MR堆叠被偏移，使得MR堆叠交错。 例如，耦合到公共字线或公共位线的MR堆叠组可以交错。 交错布局提供了对于给定MRAM阵列区域的相邻MR堆叠之间的距离增加，从而导致例如在写入操作期间串扰的减少。

公开(公告)号：US20060120147A1

公开(公告)日：2006-06-08

申请号：US10904897

申请日：2004-12-03

Applicant: Yuan-Ching Peng ,  Shyue-Shyn Lin ,  Wei-Ming Chen

Inventor： Yuan-Ching Peng ,  Shyue-Shyn Lin ,  Wei-Ming Chen

IPC: G11C11/14 ,  G11C11/00 ,  G11C11/15 ,  G11C5/02

CPC classification number: G11C11/15 ,  G11C5/063

Abstract: A magnetic random access memory (MRAM) device disclosed herein includes an array of magnetic memory cells having magnetoresistive (MR) stacks. The MRAM array also includes a series of bit lines and word lines coupled to the MR stacks. The array layout provides for reduced crosstalk between neighboring memory cells by increasing a distance between neighboring MR stacks along a common conductor without increasing the overall layout area of the MRAM array. Several embodiments are disclosed where neighboring MR stacks are offset such that the MR stacks are staggered. For example, groups of MR stacks coupled to a common word line or to a common bit line can be staggered. The staggered layout provides for increased distance between neighboring MR stacks for a given MRAM array area, thereby resulting in a reduction of crosstalk, for example during write operations.

Abstract translation: 本文公开的磁性随机存取存储器（MRAM）装置包括具有磁阻（MR）堆叠的磁存储器单元阵列。 MRAM阵列还包括耦合到MR堆叠的一系列位线和字线。 阵列布局通过增加沿着公共导体的相邻MR堆叠之间的距离而不增加MRAM阵列的总体布局面积来提供相邻存储器单元之间减少的串扰。 公开了几个实施例，其中相邻MR堆叠被偏移，使得MR堆叠交错。 例如，耦合到公共字线或公共位线的MR堆叠组可以交错。 交错布局提供了对于给定MRAM阵列区域的相邻MR堆叠之间的距离增加，从而导致例如在写入操作期间串扰的减少。

公开(公告)号：US20070145519A1

公开(公告)日：2007-06-28

申请号：US11320512

申请日：2005-12-27

Applicant: Yuan-Ching Peng ,  Chloe Chen ,  David Lwu ,  Shyue-Shyh Lin ,  Wei-Ming Chen

Inventor： Yuan-Ching Peng ,  Chloe Chen ,  David Lwu ,  Shyue-Shyh Lin ,  Wei-Ming Chen

IPC: H01L29/00

CPC classification number: H01L27/11 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/7833

Abstract: A semiconductor structure and a method of forming the same using replacement gate processes are provided. The semiconductor structure includes a butted contact coupling a source/drain region, or a silicide on the source/drain region, of a first transistor and a gate extension. The semiconductor structure further includes a contact pad over the source/drain region of the first transistor and electrically coupled to the source/drain region. The addition of the contact pad reduces the contact resistance and the possibility that an open circuit is formed between the butted contact and the source/drain region. The contact pad preferably has a top surface substantially leveled with a top surface of the gate extension.

Abstract translation: 提供半导体结构及其使用替代栅极工艺的方法。 半导体结构包括耦合第一晶体管和栅极延伸的源极/漏极区域或源极/漏极区域上的硅化物的对接触点。 半导体结构还包括在第一晶体管的源极/漏极区域上的电连接到源极/漏极区域的接触焊盘。 接触焊盘的添加减小了接触电阻以及在对接触点和源极/漏极区域之间形成开路的可能性。 接触垫优选地具有基本上与门延伸部的顶表面平齐的顶表面。

公开(公告)号：US6022457A

公开(公告)日：2000-02-08

申请号：US45980

申请日：1998-03-18

Applicant: Hsin-Yuan Huang ,  Yuan-Ching Peng ,  Lih-Juann Chen ,  Yong-Fen Hsieh

Inventor： Hsin-Yuan Huang ,  Yuan-Ching Peng ,  Lih-Juann Chen ,  Yong-Fen Hsieh

IPC: H01L21/285 ,  C23C14/34

CPC classification number: H01L21/28518

Abstract: A method of manufacturing a cobalt suicide layer in the present invention has a silicon layer formation step. The silicon layer is formed at the interface between the cobalt layer and titanium layer, therefore the interface is smoother in this invention than in other conventional methods, and there are no voids formed at the interface. Moreover, consumption of the silicon can be controlled by adjusting the thickness of the silicon layer.

Abstract translation: 本发明的硅化钴层的制造方法具有硅层形成工序。 硅层形成在钴层和钛层之间的界面处，因此本发明的界面比其它常规方法更平滑，并且在界面处没有形成空隙。 此外，可以通过调整硅层的厚度来控制硅的消耗。

公开(公告)号：US08404538B2

公开(公告)日：2013-03-26

申请号：US12572743

申请日：2009-10-02

Applicant: Kao-Ting Lai ,  Da-Wen Lin ,  Hsien-Hsin Lin ,  Yuan-Ching Peng ,  Chi-Hsi Wu

Inventor： Kao-Ting Lai ,  Da-Wen Lin ,  Hsien-Hsin Lin ,  Yuan-Ching Peng ,  Chi-Hsi Wu

IPC: H01L21/8238

CPC classification number: H01L21/3247 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.

Abstract translation: 一种方法包括提供包括衬底材料的衬底，在衬底上方的栅极电介质膜和与栅极电介质膜相邻的第一间隔物。 间隔物具有与基底的表面接触的第一部分和与栅极电介质膜的一侧接触的第二部分。 在与衬垫相邻的衬底的区域中形成凹部。 凹部由基底材料的第一侧壁限定。 第一侧壁的至少一部分位于间隔件的至少一部分的下面。 衬垫材料位于衬垫的第一部分下面被回流，使得限定凹陷的衬底材料的第一侧壁的顶部基本上与栅极电介质膜和间隔物之间​​的边界对齐。 凹陷部分填充有压力源材料。

公开(公告)号：US08372719B2

公开(公告)日：2013-02-12

申请号：US12724157

申请日：2010-03-15

Applicant: Sheng-Hsiung Wang ,  Fu-Kai Yang ,  Yuan-Ching Peng ,  Chi-Cheng Hung

Inventor： Sheng-Hsiung Wang ,  Fu-Kai Yang ,  Yuan-Ching Peng ,  Chi-Cheng Hung

IPC: H01L21/461 ,  H01L21/027

CPC classification number: H01L21/31144 ,  H01L21/28017 ,  H01L21/31116 ,  H01L29/66795

Abstract: A method of removing a hard mask during fabrication of semiconductor devices is provided. A protective layer, such as a bottom anti-reflective coating (BARC) layer or other dielectric layer, is formed over structures formed on a substrate, wherein spacers are formed alongside the structures. In an embodiment, the structures are gate electrodes having a hard mask formed thereon and the spacers are spacers formed alongside the gate electrodes. A photoresist layer is formed over the protective layer, and the photoresist layer may be patterned to remove a portion of the photoresist layer over portions of the protective layer. Thereafter, an etch-back process is performed, such that the protective layer adjacent to the spacers remains to substantially protect the spacers. The hard mask is then removed while the protective layer protects the spacers.

Abstract translation: 提供了在制造半导体器件期间去除硬掩模的方法。 在衬底上形成的结构上形成诸如底部抗反射涂层（BARC）层或其它电介质层的保护层，其中间隔物沿着结构形成。 在一个实施例中，结构是具有形成在其上的硬掩模的栅电极，并且间隔物是与栅电极一起形成的间隔物。 在保护层上形成光致抗蚀剂层，并且可以对光致抗蚀剂层进行图案化以在保护层的部分上去除光致抗蚀剂层的一部分。 此后，执行回蚀处理，使得与间隔物相邻的保护层保持基本上保护间隔物。 然后去除硬掩模，同时保护层保护间隔物。

公开(公告)号：US07349234B2

公开(公告)日：2008-03-25

申请号：US11119052

申请日：2005-04-29

Applicant: Yuan-Ching Peng ,  Shyue-Shyh Lin ,  Wei-Ming Chen

Inventor： Yuan-Ching Peng ,  Shyue-Shyh Lin ,  Wei-Ming Chen

IPC: G11C5/08

CPC classification number: G11C11/15 ,  G11C5/063

Abstract: A magnetic random access memory (MRAM) device disclosed herein includes an array of magnetic memory cells having magnetoresistive (MR) stacks. The MRAM array also includes a series of bit lines and word lines coupled to the MR stacks. The array layout provides for reduced crosstalk between neighboring memory cells by increasing a distance between neighboring MR stacks along a common conductor without increasing the overall layout area of the MRAM array. Several embodiments are disclosed where neighboring MR stacks are offset such that the MR stacks are staggered. For example, groups of MR stacks coupled to a common word line or to a common bit line can be staggered. The staggered layout provides for increased distance between neighboring MR stacks for a given MRAM array area, thereby resulting in a reduction of crosstalk, for example during write operations.

Abstract translation: 本文公开的磁性随机存取存储器（MRAM）装置包括具有磁阻（MR）堆叠的磁存储器单元阵列。 MRAM阵列还包括耦合到MR堆叠的一系列位线和字线。 阵列布局通过增加沿着公共导体的相邻MR堆叠之间的距离而不增加MRAM阵列的总体布局面积来提供相邻存储器单元之间减少的串扰。 公开了几个实施例，其中相邻MR堆叠被偏移，使得MR堆叠交错。 例如，耦合到公共字线或公共位线的MR堆叠组可以交错。 交错布局提供了对于给定MRAM阵列区域的相邻MR堆叠之间的距离增加，从而导致例如在写入操作期间串扰的减少。

公开(公告)号：US5897373A

公开(公告)日：1999-04-27

申请号：US870822

申请日：1997-06-06

Applicant: Yuan-Ching Peng ,  Lih-Juann Chen ,  Wen-Yi Hsieh ,  Jenn-Tarng Lin ,  Yong-Fen Hsieh

Inventor： Yuan-Ching Peng ,  Lih-Juann Chen ,  Wen-Yi Hsieh ,  Jenn-Tarng Lin ,  Yong-Fen Hsieh

IPC: H01L21/285 ,  H01L21/283

CPC classification number: H01L21/28518

Abstract: The present invention relates to a method of manufacturing semiconductor components having a titanium nitride layer including the steps of providing a semiconductor substrate with a transistor including a gate and source/drain regions, depositing an insulating layer above the semiconductor substrate, etching the insulating layer to form an opening exposing the source/drain region below, depositing an ultra-thin titanium nitride layer having a grainy particulate profile and a thickness of about 0.5 nm to 2 nm around the edge and at the bottom of the opening, depositing a metallic layer over various aforementioned layers, and forming a metal silicide layer by heating the semiconductor substrate to allow the metallic layer to react with silicon on the semiconductor substrate surface.

Abstract translation: 本发明涉及一种制造具有氮化钛层的半导体元件的方法，包括以下步骤：向半导体衬底提供包括栅极和源/漏区的晶体管，在半导体衬底上沉积绝缘层，将绝缘层蚀刻到 形成暴露下面的源极/漏极区域的开口，在开口的边缘和底部沉积具有粒状颗粒轮廓和约0.5nm至2nm的厚度的超薄氮化钛层，沉积金属层 各种上述层，并且通过加热半导体衬底形成金属硅化物层，以允许金属层与半导体衬底表面上的硅反应。