公开(公告)号：US20220317876A1

公开(公告)日：2022-10-06

申请号：US17218700

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan Alsop ,  Nuwan Jayasena ,  Shaizeen Aga ,  Andrew McCrabb

IPC: G06F3/06

Abstract: Methods and apparatuses to control digital data transfer via a memory channel between a memory module and a processor are disclosed. At least one of the memory module or the processor coalesces a plurality of short data words into multicast coalesced block data comprising a single data block for transfer via the memory channel. Each of the plurality of short data words pertains to one of at least two partitioned memory submodules in the memory module. The multicast coalesced block data is communicated over the memory channel.

公开(公告)号：US11409608B2

公开(公告)日：2022-08-09

申请号：US17136549

申请日：2020-12-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Shrikanth Ganapathy ,  Ross V. La Fetra ,  John Kalamatianos ,  Sudhanva Gurumurthi ,  Shaizeen Aga ,  Vilas Sridharan ,  Michael Ignatowski ,  Nuwan Jayasena

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/10

Abstract: Providing host-based error detection capabilities in a remote execution device is disclosed. A remote execution device performs a host-offloaded operation that modifies a block of data stored in memory. Metadata is generated locally for the modified of block of data such that the local metadata generation emulates host-based metadata generation. Stored metadata for the block of data is updated with the locally generated metadata for the modified portion of the block of data. When the host performs an integrity check on the modified block of data using the updated metadata, the host does not distinguish between metadata generated by the host and metadata generated in the remote execution device.

公开(公告)号：US20210182262A1

公开(公告)日：2021-06-17

申请号：US16717027

申请日：2019-12-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena

IPC: G06F16/22 ,  G06F16/31

Abstract: A method and apparatus perform a first hash operation on a first key wherein the first hash operation is biased to map the first key and associated value to a set of frequently-accessed buckets in a hash table. An entry for the first key and associated value is stored in the set of frequently-accessed buckets. A second hash operation is performed on a second key wherein the second hash operation is biased to map the second key and associated value to a set of less frequently-accessed buckets in the hash table. An entry for the second key and associated value is stored in the set of less frequently-accessed buckets. The method and apparatus perform a hash table look up of the requested key in the set of frequently-accessed buckets, if the requested key is not found, then a hash table lookup is performed in the set of less frequently-accessed buckets.

公开(公告)号：US10956536B2

公开(公告)日：2021-03-23

申请号：US16176662

申请日：2018-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena ,  Allen H. Rush ,  Michael Ignatowski

IPC: G06F17/16 ,  G06F7/53 ,  G06F15/80

Abstract: A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a sub-portion of data of a first matrix and a sub-portion of data of a second matrix. The processor cores are also configured to determine a product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core, another sub-portion of data of the second matrix and determine a product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.

公开(公告)号：US20210050864A1

公开(公告)日：2021-02-18

申请号：US16542872

申请日：2019-08-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander D. Breslow ,  Nuwan Jayasena ,  John Kalamatianos

IPC: H03M7/40 ,  G06F7/08 ,  G06F3/06

Abstract: A data processing platform, method, and program product perform compression and decompression of a set of data items. Suffix data and a prefix are selected for each respective data item in the set of data items based on data content of the respective data item. The set of data items is sorted based on the prefixes. The prefixes are encoded by querying multiple encoding tables to create a code word containing compressed information representing values of all prefixes for the set of data items. The code word and suffix data for each of the data items are stored in memory. The code word is decompressed to recover the prefixes. The recovered prefixes are paired with their respective suffix data.

公开(公告)号：US10902087B2

公开(公告)日：2021-01-26

申请号：US16176678

申请日：2018-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena ,  Allen H. Rush ,  Michael Ignatowski

IPC: G06F17/16 ,  G06F15/80 ,  G06F7/53

Abstract: A processing device is provided which includes memory and a processor comprising a plurality of processor cores in communication with each other via first and second hierarchical communication links. Each processor core in a group of the processor cores is in communication with each other via the first hierarchical communication links. Each processor core is configured to store, in the memory, one of a plurality of sub-portions of data of a first matrix, store, in the memory, one of a plurality of sub-portions of data of a second matrix, determine an outer product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core of the group of processor cores, another sub-portion of data of the second matrix and determine another outer product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.

公开(公告)号：US20200081651A1

公开(公告)日：2020-03-12

申请号：US16123837

申请日：2018-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena

IPC: G06F3/06 ,  G06F11/10

Abstract: Methods, systems, and devices for near-memory data-dependent gathering and packing of data stored in a memory. A processing device extracts a function, a memory source address, and a memory destination address from a near-memory data-dependent gathering and packing primitive. A signal to perform gathering and packing operations based on the primitive is sent to near-memory processing circuitry of a memory device. The near-memory processing circuitry receives the signal, gathers data from the memory device based on the function and the memory source address, and packs the gathered data into the memory device based on the memory destination address.

公开(公告)号：US10579557B2

公开(公告)日：2020-03-03

申请号：US15872943

申请日：2018-01-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Michael Ignatowski

IPC: G06F13/16 ,  G06F3/06

Abstract: A configurable computing system which uses near-memory and in-memory hardened logic blocks is described herein. The hardened logic blocks are incorporated into memory modules. The memory modules include an interface or communication logic to communicate between the configurable computing substrate and the memory module. In an implementation, the memory modules can include an on-die memory or other forms of non-configurable logic to enable more efficient processing for a variety of operations. In another implementation, the memory modules can include a portion of configurable computing substrate logic fabric to enable more efficient processing for a variety of operations. In another implementation, the memory modules can include an on-die memory and a portion of configurable computing substrate logic fabric to enable more efficient processing for a variety of operations.

公开(公告)号：US20170357583A1

公开(公告)日：2017-12-14

申请号：US15181415

申请日：2016-06-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Boyer ,  Gabriel Loh ,  Nuwan Jayasena

IPC: G06F12/0804 ,  G06F12/0842 ,  G06F12/0806

CPC classification number: G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F2212/1016 ,  G06F2212/502 ,  G06F2212/70

Abstract: Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.

公开(公告)号：US20170085472A1

公开(公告)日：2017-03-23

申请号：US14859844

申请日：2015-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Michael Ignatowski ,  Nuwan Jayasena ,  Gabriel H. Loh

IPC: H04L12/781 ,  H04L12/715 ,  H04L12/861 ,  H04L29/06

CPC classification number: H04L45/52 ,  H04L45/04 ,  H04L49/9057 ,  H04L69/08

Abstract: A communication device includes a data source that generates data for transmission over a bus, and a data encoder that receives and encodes outgoing data. An encoder system receives outgoing data from a data source and stores the outgoing data in a first queue. An encoder encodes outgoing data with a header type that is based upon a header type indication from a controller and stores the encoded data that may be a packet or a data word with at least one layered header in a second queue for transmission. The device is configured to receive at a payload extractor, a packet protocol change command from the controller and to remove the encoded data and to re-encode the data to create a re-encoded data packet and placing the re-encoded data packet in the second queue for transmission.