公开(公告)号：US20210382718A1

公开(公告)日：2021-12-09

申请号：US16895825

申请日：2020-06-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Varun Agrawal ,  John Kalamatianos

IPC: G06F9/30 ,  G06F9/38

Abstract: An electronic device includes a processor, a branch predictor in the processor, and a predictor controller in the processor. The branch predictor includes multiple prediction functional blocks, each prediction functional block configured for generating predictions for control transfer instructions (CTIs) in program code based on respective prediction information, the branch predictor configured to select, from among predictions generated by the prediction functional blocks for each CTI, a selected prediction to be used for that CTI. The predictor controller keeps a record of prediction functional blocks from which the branch predictor previously selected predictions for CTIs. The predictor controller uses information from the record for controlling which prediction functional blocks are used by the branch predictor for generating predictions for CTIs.

公开(公告)号：US12175073B2

公开(公告)日：2024-12-24

申请号：US17139496

申请日：2020-12-31

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Varun Agrawal ,  Niti Madan

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods for reusing remote registers in processing in memory (PIM) are disclosed. A system includes at least a host processor, a memory controller, and a PIM device. When the memory controller receives, from the host processor, an operation targeting the PIM device, the memory controller determines whether an optimization can be applied to the operation. The memory controller converts the operation into N PIM commands if the optimization is not applicable. Otherwise, the memory controller converts the operation into a N−1 PIM commands if the optimization is applicable. For example, if the operation involves reusing a constant value, a copy command can be omitted, resulting in memory bandwidth reduction and power consumption savings. In one scenario, the memory controller includes a constant-value cache, and the memory controller performs a lookup of the constant-value cache to determine if the optimization is applicable for a given operation.

公开(公告)号：US20240330186A1

公开(公告)日：2024-10-03

申请号：US18192925

申请日：2023-03-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Travis Henry Boraten ,  Varun Agrawal

IPC: G06F12/0817

CPC classification number: G06F12/0817

Abstract: Cache directory lookup address augmentation techniques are described. In one example, a system includes a cache system including a plurality of cache levels and a cache coherence controller. The cache coherence controller is configured to perform a cache directory lookup using a cache directory. The cache directory lookup is configured to indicate whether data associated with a memory address specified by a memory request is valid in memory. The cache directory lookup is augmented to include an additional memory address based on the memory address.

公开(公告)号：US12026401B2

公开(公告)日：2024-07-02

申请号：US17855109

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Niti Madan ,  Yasuko Eckert ,  Varun Agrawal ,  John Kalamatianos

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679

Abstract: In accordance with described techniques for DRAM row management for processing in memory, a plurality of instructions are obtained for execution by a processing in memory component embedded in a dynamic random access memory. An instruction is identified that last accesses a row of the dynamic random access memory, and a subsequent instruction is identified that first accesses an additional row of the dynamic random access memory. A first command is issued to close the row and a second command is issued to open the additional row after the row is last accessed by the instruction.

公开(公告)号：US11550588B2

公开(公告)日：2023-01-10

申请号：US16109195

申请日：2018-08-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kalamatianos ,  Adithya Yalavarti ,  Varun Agrawal ,  Subhankar Pal ,  Vinesh Srinivasan

IPC: G06F9/38 ,  G06F11/34 ,  G06F1/32 ,  G06F1/3287

Abstract: A branch predictor of a processor includes one or more prediction structures, including a predicted branch address and predicted branch direction, that identify predicted branches. To reduce power consumption, the branch predictor selects one or more of the prediction structures that are not expected to provide useful branch prediction information and filters the selected structures such that the filtered structures are not used for branch prediction. The branch predictor thereby reduces the amount of power used for branch prediction without substantially reducing the accuracy of the predicted branches.