公开(公告)号：US20200150966A1

公开(公告)日：2020-05-14

申请号：US16725203

申请日：2019-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Varun Agrawal ,  John Kalamatianos ,  Adithya Yalavarti ,  Jingjie Qian

IPC: G06F9/38

Abstract: An electronic device handles accesses of a branch prediction functional block when executing instructions in program code. The electronic device includes a processor having the branch prediction functional block that provides branch prediction information for control transfer instructions (CTIs) in the program code and a minimum predictor use (MPU) functional block. The MPU functional block determines, based on a record associated with a given fetch group of instructions, that a specified number of subsequent fetch groups of instructions that were previously determined to include no CTIs or conditional CTIs that were not taken are to be fetched for execution in sequence following the given fetch group. The MPU functional block then, when each of the specified number of the subsequent fetch groups is fetched and prepared for execution, prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that subsequent fetch group.

公开(公告)号：US11550588B2

公开(公告)日：2023-01-10

申请号：US16109195

申请日：2018-08-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kalamatianos ,  Adithya Yalavarti ,  Varun Agrawal ,  Subhankar Pal ,  Vinesh Srinivasan

IPC: G06F9/38 ,  G06F11/34 ,  G06F1/32 ,  G06F1/3287

Abstract: A branch predictor of a processor includes one or more prediction structures, including a predicted branch address and predicted branch direction, that identify predicted branches. To reduce power consumption, the branch predictor selects one or more of the prediction structures that are not expected to provide useful branch prediction information and filters the selected structures such that the filtered structures are not used for branch prediction. The branch predictor thereby reduces the amount of power used for branch prediction without substantially reducing the accuracy of the predicted branches.

公开(公告)号：US20180052778A1

公开(公告)日：2018-02-22

申请号：US15243921

申请日：2016-08-22

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Adithya Yalavarti ,  Johnsy Kanjirapallil John

IPC: G06F12/12 ,  G06F12/0864 ,  G06F12/0893 ,  G06F12/0891

CPC classification number: G06F12/12 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0864 ,  G06F12/0893 ,  G06F12/128 ,  G06F2212/1024

Abstract: A processing apparatus and a method of accessing data using cache hot set detection is provided that includes receiving a plurality of requests to access data in a cache. The cache includes a plurality of cache sets each including N number of cache lines. Each request includes an address. The apparatus and a method also includes storing, in a HSVC array, cache line victims of one or more of the plurality of cache sets determined to be hot sets. Each cache line victim includes a corresponding address that is determined, using a HSD array, to belong to the one or more determined cache hot sets based on a hot set frequency of a plurality of addresses mapped to the set in the cache.

公开(公告)号：US11513801B2

公开(公告)日：2022-11-29

申请号：US16127093

申请日：2018-09-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Adithya Yalavarti ,  John Kalamatianos ,  Matthew R. Poremba

IPC: G06F9/38 ,  G06F1/3287 ,  G06F9/30

Abstract: An electronic device is described that handles control transfer instructions (CTIs) when executing instructions in program code. The electronic device has a processor that includes a branch prediction functional block and a sequential fetch logic functional block. The sequential fetch logic functional block determines, based on a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for execution in sequence following the CTI. When each of the specified number of fetch groups is fetched and prepared for execution, the sequential fetch logic prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group.

公开(公告)号：US10853075B2

公开(公告)日：2020-12-01

申请号：US16725203

申请日：2019-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Varun Agrawal ,  John Kalamatianos ,  Adithya Yalavarti ,  Jingjie Qian

IPC: G06F9/30 ,  G06F9/38

Abstract: An electronic device handles accesses of a branch prediction functional block when executing instructions in program code. The electronic device includes a processor having the branch prediction functional block that provides branch prediction information for control transfer instructions (CTIs) in the program code and a minimum predictor use (MPU) functional block. The MPU functional block determines, based on a record associated with a given fetch group of instructions, that a specified number of subsequent fetch groups of instructions that were previously determined to include no CTIs or conditional CTIs that were not taken are to be fetched for execution in sequence following the given fetch group. The MPU functional block then, when each of the specified number of the subsequent fetch groups is fetched and prepared for execution, prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that subsequent fetch group.

公开(公告)号：US20200081716A1

公开(公告)日：2020-03-12

申请号：US16127093

申请日：2018-09-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Adithya Yalavarti ,  John Kalamatianos ,  Matthew R. Poremba

IPC: G06F9/38 ,  G06F9/30 ,  G06F1/32

Abstract: An electronic device is described that handles control transfer instructions (CTIs) when executing instructions in program code. The electronic device has a processor that includes a branch prediction functional block and a sequential fetch logic functional block. The sequential fetch logic functional block determines, based on a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for execution in sequence following the CTI. When each of the specified number of fetch groups is fetched and prepared for execution, the sequential fetch logic prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group.