公开(公告)号：US12119312B2

公开(公告)日：2024-10-15

申请号：US18223525

申请日：2023-07-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Nan Lin ,  Wei-Tung Chang ,  Jen-Chieh Kao ,  Huei-Shyong Cho

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01Q1/22 ,  H01Q1/24

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/1421 ,  H01Q1/243

Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.

公开(公告)号：US11705412B2

公开(公告)日：2023-07-18

申请号：US17347220

申请日：2021-06-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Nan Lin ,  Wei-Tung Chang ,  Jen-Chieh Kao ,  Huei-Shyong Cho

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01Q1/22 ,  H01L23/00 ,  H01Q1/24

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/1421 ,  H01Q1/243

Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.

公开(公告)号：US11316274B2

公开(公告)日：2022-04-26

申请号：US16432662

申请日：2019-06-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Nan Lin ,  Hsu-Nan Fang

IPC: H01Q1/38 ,  H01Q13/18 ,  H01L23/31 ,  H01L23/66 ,  H01L23/29 ,  H01L23/498 ,  H01L21/56 ,  H01L23/13

Abstract: A semiconductor device package includes a substrate, a first molding compound and antenna layer. The substrate has a first surface and a second surface opposite to the first surface. The first molding compound is disposed on the first surface of the substrate. The antenna layer is disposed on the first molding compound. The substrate, the first molding compound and the antenna layer define a cavity.

公开(公告)号：US09653407B2

公开(公告)日：2017-05-16

申请号：US14791043

申请日：2015-07-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shih-Ren Chen ,  Cheng-Nan Lin

IPC: H01L23/00 ,  H01L23/552 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00012

Abstract: The present disclosure relates to a semiconductor device package and a method for manufacturing the semiconductor device package. The semiconductor device package includes a substrate, a grounding element, a component, a package body and a conductive layer. The grounding element is disposed in the substrate and includes a connection surface exposed at a second portion of a lateral surface of the substrate. The component is disposed on a top surface of the substrate. The package body covers the component and the top surface of the substrate. A lateral surface of the package body is aligned with the lateral surface of the substrate. The conductive layer covers a top surface and the lateral surface of the package body, and further covers the second portion of the lateral surface of the substrate. A first portion of the lateral surface of the substrate is exposed from the conductive layer.

公开(公告)号：US09269673B1

公开(公告)日：2016-02-23

申请号：US14521342

申请日：2014-10-22

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： I-Chia Lin ,  Chieh-Chen Fu ,  Kuo-Hsien Liao ,  Cheng-Nan Lin

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/60

CPC classification number: H01L23/552 ,  H01L23/13 ,  H01L23/31 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49822 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2924/15159 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00012

Abstract: A semiconductor device package includes a substrate, at least one component, a package body, a first conductive layer, a first shielding layer, a second shielding layer and a second conductive layer. The component is disposed on a first surface of the substrate. The package body is disposed on the first surface of the substrate and covers the component. The first conductive layer covers the package body and at least a portion of the substrate. The first shielding layer covers the first conductive layer and has a first thickness and includes a high conductivity material. The second shielding layer covers the first shielding layer and has a second thickness and includes a high permeability material. A ratio of the first thickness to the second thickness being in a range of 0.2 to 3. The second conductive layer covers the second shielding layer.

Abstract translation: 半导体器件封装包括衬底，至少一个部件，封装体，第一导电层，第一屏蔽层，第二屏蔽层和第二导电层。 该部件设置在基板的第一表面上。 包装体设置在基板的第一表面上并覆盖该部件。 第一导电层覆盖封装主体和衬底的至少一部分。 第一屏蔽层覆盖第一导电层并且具有第一厚度并且包括高导电性材料。 第二屏蔽层覆盖第一屏蔽层并且具有第二厚度并且包括高磁导率材料。 第一厚度与第二厚度的比率在0.2至3的范围内。第二导电层覆盖第二屏蔽层。