公开(公告)号：US09653029B2

公开(公告)日：2017-05-16

申请号：US14558663

申请日：2014-12-02

Applicant: Apple Inc.

Inventor： Chaohao Wang ,  Szu-Hsien Lee ,  Paolo Sacchetto ,  Shih Chang Chang ,  Chun-Yao Huang ,  Paul S. Drzaic

IPC: G09G3/36 ,  G09G3/32

CPC classification number: G09G3/3611 ,  G09G3/32 ,  G09G2310/04 ,  G09G2320/0247 ,  G09G2320/103 ,  G09G2340/0435

Abstract: This application relates to methods and apparatus for refreshing a display device at various frequencies. Specifically, multiple areas of the display device can be refreshed concurrently at different frequencies. In this way, when static content is being displayed in certain areas of the display device, those certain areas can be refreshed at a lower rate than areas displaying dynamic content such as video or animation. By refreshing at lower rates, the energy consumed by the display device and subsystems associated with the display device can be reduced. Additionally, processes for reducing flicker when refreshing the display device at different refresh rates are disclosed herein.

公开(公告)号：US20170004790A1

公开(公告)日：2017-01-05

申请号：US14862071

申请日：2015-09-22

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Shih Chang Chang ,  Szu-Hsien Lee

IPC: G09G3/36 ,  G09G3/32

CPC classification number: G09G3/3674 ,  G09G3/20 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0291

Abstract: A display is provided that includes an array of display pixels and gate driver circuitry for providing data and gate line signals to the display pixels. Gate driver circuitry may include gate driver circuits that generate the gate line signals. A gate driver circuit may include at least a buffer transistor, a bootstrapping capacitor coupled to the buffer transistor, a pulldown transistor coupled in series with the buffer transistor, and an isolation transistor coupled to the gate of the pulldown transistor. The buffer transistor may directly receive a first clock signal, whereas the isolation transistor may directly receive a second clock signal that is complementary to the first clock signal. The pulldown transistor is substantially larger than the buffer transistor. The buffer transistor is substantially larger than the isolation transistor. Configured as such, clock loading is minimized while the pulldown transistor is sized to provide the desired fall time performance.

Abstract translation: 提供了一种显示器，其包括用于向显示像素提供数据和栅极线信号的显示像素阵列和栅极驱动器电路。 栅极驱动器电路可以包括产生栅极线信号的栅极驱动器电路。 栅极驱动器电路可以包括至少缓冲晶体管，耦合到缓冲晶体管的自举电容器，与缓冲晶体管串联耦合的下拉晶体管，以及耦合到下拉晶体管的栅极的隔离晶体管。 缓冲晶体管可以直接接收第一时钟信号，而隔离晶体管可以直接接收与第一时钟信号互补的第二时钟信号。 下拉晶体管实质上大于缓冲晶体管。 缓冲晶体管基本上大于隔离晶体管。 如此配置，时钟负载最小化，而下拉晶体管的尺寸设置为提供所需的下降时间性能。

公开(公告)号：US20160293081A1

公开(公告)日：2016-10-06

申请号：US14677531

申请日：2015-04-02

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Chun-Yao Huang ,  Shih Chang Chang ,  Szu-Hsien Lee

IPC: G09G3/20 ,  G06F3/044 ,  G06F3/042 ,  G06F3/041

CPC classification number: G06F3/0416 ,  G09G3/3677 ,  G09G2310/0202 ,  G09G2310/0218 ,  G09G2310/0267 ,  G09G2320/043

Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include blocks of gate driver circuits each having an output coupled to a respective one of the gate lines. The gate driver circuits of each block are coupled in a chain to form a shift register. Each block has a local block-level gate start pulse generator. The display driver circuitry has a display driver circuit that supplies a gate start pulse clock to each of the local block-level gate start pulse generators. The local block-level gate start pulse generators create gate start pulses that are applied to the first gate driver circuit in each shift register. The display driver circuit may delay the gate start pulse clock when it is desired to implement an intraframe pause.

Abstract translation: 显示器可以具有由显示驱动器电路控制的像素阵列。 栅极驱动器电路将栅极线信号提供给像素的行。 栅极驱动器电路可以包括栅极驱动器电路块，每个栅极驱动器电路具有耦合到相应的一条栅极线的输出。 每个块的栅极驱动器电路被耦合在链中以形成移位寄存器。 每个块具有本地块级门控起始脉冲发生器。 显示驱动器电路具有显示驱动器电路，其向每个本地块级门控起始脉冲发生器提供栅极起始脉冲时钟。 局部块电平门起始脉冲发生器产生施加到每个移位寄存器中的第一栅极驱动器电路的栅极起始脉冲。 当期望实现帧内暂停时，显示驱动器电路可以延迟门启动脉冲时钟。

公开(公告)号：US09367188B2

公开(公告)日：2016-06-14

申请号：US14286718

申请日：2014-05-23

Applicant: Apple Inc.

Inventor： Szu-Hsien Lee ,  Byung Duk Yang ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Shih Chang Chang

IPC: G06F3/044

CPC classification number: G06F3/044 ,  G06F3/0416 ,  Y10T29/49107

Abstract: A touch screen. In some examples, the touch screen can comprise a first element coupled to a first sense connection, and a second element coupled to a second sense connection. In some examples, the first and second sense connections can be configured such that a load presented by the first sense connection and the first element is substantially equal to a load presented by the second sense connection and the second element. In some examples, the first and second sense connections can comprise detour routing configured such that a resistance of the first sense connection is substantially equal to a resistance of the second sense connection. In some examples, the first and second sense connections can be coupled to dummy routing configured such that a first capacitance presented by the first sense connection is substantially equal to a second capacitance presented by the second sense connection.

Abstract translation: 触摸屏。 在一些示例中，触摸屏可以包括耦合到第一感测连接的第一元件和耦合到第二感测连接的第二元件。 在一些示例中，第一和第二感测连接可以被配置为使得由第一感测连接和第一元件呈现的负载基本上等于由第二感测连接和第二元件呈现的负载。 在一些示例中，第一和第二感测连接可以包括被配置为使得第一感测连接的电阻基本上等于第二感测连接的电阻的迂回路由。 在一些示例中，第一感测连接和第二感测连接可以耦合到伪路由，其被配置为使得由第一感测连接呈现的第一电容基本上等于由第二感测连接呈现的第二电容。

公开(公告)号：US20150055047A1

公开(公告)日：2015-02-26

申请号：US14228070

申请日：2014-03-27

Applicant: Apple Inc.

Inventor： Shih Chang Chang ,  Ming-Chin Hung ,  Cheng-Ho Yu ,  Ting-Kuo Chang ,  Abbas Jamshidi Roudbari ,  Shang-Chih Lin ,  Kyung-Wook Kim ,  Chun-Yao Huang ,  Szu-Hsien Lee ,  Yu-Cheng Chen ,  Hiroshi Osawa

IPC: G02F1/1368

CPC classification number: H01L27/3262 ,  G02F1/13454 ,  G02F1/13624 ,  G02F1/1368 ,  G02F2001/13685 ,  G02F2202/104 ,  G09G3/3225 ,  G09G3/3611 ,  G09G3/3677 ,  G09G2320/043 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1255

Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.

Abstract translation: 电子设备可以包括在基板上具有显示像素阵列的显示器。 显示像素可以是液晶显示器中的有机发光二极管显示像素或显示像素。 在有机发光二极管显示器中，可以形成包括半导体氧化物薄膜晶体管，硅薄膜晶体管和电容器结构的混合薄膜晶体管结构。 电容器结构可以与半导体氧化物薄膜晶体管重叠。 有机发光二极管显示像素可以具有氧化物和硅晶体管的组合。 在液晶显示器中，显示驱动器电路可以包括硅薄膜晶体管电路，显示像素可以基于氧化物薄膜晶体管。 可以在形成硅晶体管栅极和氧化物晶体管栅极中使用单层或两层不同的栅极金属层。 硅晶体管可以具有与浮动栅极结构重叠的栅极。

公开(公告)号：US20240420643A1

公开(公告)日：2024-12-19

申请号：US18654541

申请日：2024-05-03

Applicant: Apple Inc.

Inventor： Hao-Lin Chiu ,  Chin-Wei Lin ,  Shinya Ono ,  Kyung Wook Kim ,  Szu-Hsien Lee ,  Pei-En Chang ,  Kwang Soon Park

IPC: G09G3/3266 ,  H01L27/12 ,  H01L29/786

Abstract: A driver circuit configured to output a control signal to a row of display pixels is provided. The driver circuit can include a first transistor having a drain terminal coupled to a first positive power supply line, a gate terminal, and a source terminal that is coupled to an output port of the driver circuit on which the control signal is generated and a second transistor having a drain terminal coupled to the output port of the driver circuit, a gate terminal, and a source terminal that is coupled to a first ground power supply line. The first and second transistors can be coupled to a plurality of transistors coupled between a second positive power supply line and a second ground power supply line, configured to receive one or more clocks signals, and at least some of which include bottom gate terminals.

公开(公告)号：US20240086014A1

公开(公告)日：2024-03-14

申请号：US18514934

申请日：2023-11-20

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Donggeon Han ,  Jason N Gomez ,  Kyung Wook Kim ,  Nikolaus Hammler ,  Pei-En Chang ,  Saman Saeedi ,  Shih Chang Chang ,  Shinya Ono ,  Suk Won Hong ,  Szu-Hsien Lee ,  Victor H Yin ,  Young-Jik Jo ,  Yu-Heng Cheng ,  Joyan G Sanctis ,  Hongwoo Lee

IPC: G06F3/041 ,  G06F3/044 ,  H10K59/40

CPC classification number: G06F3/04182 ,  G06F3/044 ,  H10K59/40 ,  G06F3/0412 ,  G06F2203/04107 ,  G06F2203/04112

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The shielding layers may include shielding structures such as a conductive mesh structure and/or a transparent conductive film. The shielding structures may be actively driven or passively biased. In the active driving scheme, one or more inverting circuits may receive a noise signal from a cathode layer in the display and/or from the shielding structures, invert the received noise signal, and drive the inverted noise signal back onto the shielding structures to prevent any noise from the display from negatively impacting the performance of the touch sensors. In the passive biasing scheme, the shielding structures may be biased to a power supply voltage.

公开(公告)号：US20200074912A1

公开(公告)日：2020-03-05

申请号：US16234127

申请日：2018-12-27

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Szu-Hsien Lee

IPC: G09G3/20 ,  G09G3/3266 ,  G09G3/36

Abstract: The disclosure is related to head-to-head (H2H) gate on arrays (GOA) for pixel-based displays that may have reduced dimensions. In the described embodiments, the H2H design with alternate logic may be used to drive groups of pixels (e.g., a pixel row or column) with a primary and a secondary driver, located in opposite ends of the bezel of the electronic device. In the alternate-logic design, a shared shift-register may be used to enable two rows or columns. Embodiments in which more than two rows or columns are controlled by a single shift register are also described.

公开(公告)号：US09727165B2

公开(公告)日：2017-08-08

申请号：US14677531

申请日：2015-04-02

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Chun-Yao Huang ,  Shih Chang Chang ,  Szu-Hsien Lee

IPC: G06F3/041 ,  G09G3/36

CPC classification number: G06F3/0416 ,  G09G3/3677 ,  G09G2310/0202 ,  G09G2310/0218 ,  G09G2310/0267 ,  G09G2320/043

Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include blocks of gate driver circuits each having an output coupled to a respective one of the gate lines. The gate driver circuits of each block are coupled in a chain to form a shift register. Each block has a local block-level gate start pulse generator. The display driver circuitry has a display driver circuit that supplies a gate start pulse clock to each of the local block-level gate start pulse generators. The local block-level gate start pulse generators create gate start pulses that are applied to the first gate driver circuit in each shift register. The display driver circuit may delay the gate start pulse clock when it is desired to implement an intraframe pause.

公开(公告)号：US09564478B2

公开(公告)日：2017-02-07

申请号：US14228070

申请日：2014-03-27

Applicant: Apple Inc.

Inventor： Shih Chang Chang ,  Ming-Chin Hung ,  Cheng-Ho Yu ,  Ting-Kuo Chang ,  Abbas Jamshidi Roudbari ,  Shang-Chih Lin ,  Kyung-Wook Kim ,  Chun-Yao Huang ,  Szu-Hsien Lee ,  Yu-Cheng Chen ,  Hiroshi Osawa

IPC: G02F1/136 ,  G02F1/1345 ,  H01L27/32 ,  H01L27/12 ,  G09G3/36 ,  G02F1/1368 ,  G09G3/32 ,  G02F1/1362

CPC classification number: H01L27/3262 ,  G02F1/13454 ,  G02F1/13624 ,  G02F1/1368 ,  G02F2001/13685 ,  G02F2202/104 ,  G09G3/3225 ,  G09G3/3611 ,  G09G3/3677 ,  G09G2320/043 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1255

Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.

Abstract translation: 电子设备可以包括在基板上具有显示像素阵列的显示器。 显示像素可以是液晶显示器中的有机发光二极管显示像素或显示像素。 在有机发光二极管显示器中，可以形成包括半导体氧化物薄膜晶体管，硅薄膜晶体管和电容器结构的混合薄膜晶体管结构。 电容器结构可以与半导体氧化物薄膜晶体管重叠。 有机发光二极管显示像素可以具有氧化物和硅晶体管的组合。 在液晶显示器中，显示驱动器电路可以包括硅薄膜晶体管电路，显示像素可以基于氧化物薄膜晶体管。 可以在形成硅晶体管栅极和氧化物晶体管栅极中使用单层或两层不同的栅极金属层。 硅晶体管可以具有与浮动栅极结构重叠的栅极。