公开(公告)号：US09678889B2

公开(公告)日：2017-06-13

申请号：US14579483

申请日：2014-12-22

Applicant: ARM Limited

Inventor： Roko Grubisic ,  Andrew Burdass ,  Daren Croxford ,  Isidoros Sideris

IPC: G06F12/00 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/304 ,  Y02D10/13

Abstract: Address translation circuitry and a method of operating such a translation circuitry are provided. The address translation circuitry is configured to receive a first address used in a first addressing system and to translate it into a second address used in a second addressing system. Translation pipeline circuitry has plural pipeline stages configured to translate the first address into the second address over the course of the plural pipeline stages. Address comparison circuitry is configured to identify an address match condition when a received first address at least partially matches a previously received first address. Insertion circuitry is configured to determine a stage of progress of the previously received first address in the plural pipeline stages and to cause content of the stage of progress of the previously received first address to be unchanged at a next pipeline cycle when the address comparison circuitry identifies the address match condition.

公开(公告)号：US20240036874A1

公开(公告)日：2024-02-01

申请号：US18357503

申请日：2023-07-24

Applicant: Arm Limited

Inventor： Daren Croxford ,  Isidoros Sideris

IPC: G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/3867

Abstract: A data processor is disclosed in which groups of execution threads comprising a thread group can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. In response to an execution thread issuing circuit determining whether a portion of active threads of a first thread group and a portion of active threads of a second thread group use different execution lanes of the plurality of execution lanes, the execution thread issuing circuit issuing both the portion of active threads of a first thread group and a portion of active threads of a second thread group for execution. This can have the effect of increasing data processor efficiency, thereby increasing throughput and reducing latency.

公开(公告)号：US10748236B2

公开(公告)日：2020-08-18

申请号：US16117098

申请日：2018-08-30

Applicant: ARM Limited

Inventor： Stephane Forey ,  Isidoros Sideris ,  Reimar Gisbert Döffinger

IPC: G06F1/20 ,  G06F9/38 ,  G06T1/20 ,  G06F9/52 ,  G06F9/48

Abstract: A warp processing unit controls, in dependence on a warp program counter shared between a plurality of threads processing respective graphics fragments, fetching of a next instruction to be executed for at least some of the plurality of threads. In response to a determination that a given subset of threads is to be discarded when at least one other subset of threads is to continue, the warp processing unit processes the given subset of threads in a discarded state. For a thread processed in the discarded state, execution of instructions continues for the discarded thread, and at least one of: generation of data access messages triggered by the discarded thread is suppressed; and at least one processing operation, which would be deferred until completion of the discarded thread had the thread not been discarded, is enabled to be commenced independently of an outcome of the discarded thread.

公开(公告)号：US09953444B2

公开(公告)日：2018-04-24

申请号：US14874829

申请日：2015-10-05

Applicant: ARM LIMITED

Inventor： Isidoros Sideris ,  Michel Patrick Gabriel Emil Iwaniec ,  Andrew Burdass ,  Nebojsa Makljenovic ,  Andreas Due Engh-Halstvedt

IPC: G06T11/40 ,  G06T15/00 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06T11/40 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/005 ,  G06T15/40 ,  G06T15/405 ,  G06T2207/20021

Abstract: A graphics processing apparatus and method of performing graphics processing are provided. The graphics processing apparatus comprises a sequence of processing stages capable of performing graphics processing to generate a frame of display data. The graphics processing is performed on a tile-by-tile basis. The graphics processing apparatus is capable of determining if a current tile subject to the graphics processing is empty. At least one processing stage of the sequence of processing stages is omitted for graphics processing of the current tile in dependence on whether the current tile is empty.

公开(公告)号：US09933841B2

公开(公告)日：2018-04-03

申请号：US14664241

申请日：2015-03-20

Applicant: ARM LIMITED

Inventor： Isidoros Sideris ,  Daren Croxford ,  Andrew Burdass

IPC: G06F1/32 ,  G06F9/34 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F1/3287 ,  G06F1/3243 ,  G06F9/30181 ,  G06F9/34 ,  G06F9/3826 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3887 ,  Y02D10/152 ,  Y02D50/20

Abstract: A data processing apparatus has control circuitry for detecting whether a current micro-operation to be processed by processing circuitry is for the same data processing operation and specifies the same at least one operand as the last valid micro-operation processed by the processing circuitry. If so, then the control circuitry prevents the processing circuitry processing the current micro-operation so that an output register is not updated in response to the current micro-operation, and outputs the current value stored in the output register as the result of the current micro-operation. This allows power consumption to be reduced or performance to be improved by not repeating the same computation.