公开(公告)号：US20190096027A1

公开(公告)日：2019-03-28

申请号：US15714037

申请日：2017-09-25

Applicant: Arm Limited

Inventor： Edvard Fielding ,  Jakob Axel Fries

IPC: G06T1/60 ,  G06T1/20 ,  G06T15/00 ,  G06F12/0811

Abstract: A graphics processing system includes a cache system for transferring texture data stored in memory to a graphics processing unit for use by the graphics processing unit when generating a render output. The cache system includes a first cache operable to receive texture data from the memory system, and a second cache operable to receive texture data from the first cache and to provide texture data to the graphics processing unit for use when generating a render output, and a data processing unit intermediate the first cache and the second cache and operable to process data stored in the first cache and to store the processed data in the second cache.

公开(公告)号：US10068309B2

公开(公告)日：2018-09-04

申请号：US15254079

申请日：2016-09-01

Applicant: ARM LIMITED

Inventor： Jakob Axel Fries ,  Henrik Nils-Sture Olsson ,  Oskar Flordal ,  Sharjeel Saeed

IPC: G06T1/20 ,  G06T1/60 ,  H04N19/426 ,  H04N19/436

Abstract: An interface apparatus and method of operating the same are provided. The interface apparatus receives an uncompressed image data read request using a first addressing scheme at a first bus interface and transmits a compressed image data read request using a second addressing scheme from a second bus interface. Address translation circuitry translates between the first addressing scheme and the second addressing scheme. Decoding circuitry decodes a set of compressed image data received via the second bus interface to generate the set of uncompressed image data which is then transmitted via the first bus interface. The use of a second addressing scheme and image data compression is thus transparent to the source of the uncompressed image data read request, and the interface apparatus can therefore be used to connect devices which use different addressing schemes and image data formats, without either needing to be modified.

公开(公告)号：US10001941B2

公开(公告)日：2018-06-19

申请号：US15469503

申请日：2017-03-25

Applicant: ARM Limited

Inventor： Lars Oskar Flordal ,  Toni Viki Brkic ,  Jakob Axel Fries

IPC: G09G5/393 ,  G06T11/40 ,  G06F3/06 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0673 ,  G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T2210/08 ,  G09G5/393 ,  G09G2360/12 ,  G09G2360/122

Abstract: A tile-based graphics processing pipeline includes rendering circuitry for rendering graphics fragments to generate rendered fragment data. Each graphics fragment has associated with it a set of sampling positions to be rendered. The pipeline also includes a tile buffer configured to store rendered fragment data for sampling positions prior to the rendered fragment data being written out to memory, write out circuitry configured to write a compressed representation of the rendered fragment data for a tile in the tile buffer to memory, and processing circuitry. The processing circuitry identities, based on the writing of rendered fragment data to the tile buffer, any blocks comprising sampling positions within a tile having the same data value associated with each sampling position in the block, and to, when such a block of sampling positions is identified, trigger the write out circuitry to write a compressed representation of the block to the memory.

公开(公告)号：US20240371074A1

公开(公告)日：2024-11-07

申请号：US18602583

申请日：2024-03-12

Applicant: Arm Limited

Inventor： Richard Edward Bruce ,  Jakob Axel Fries

IPC: G06T15/06 ,  G06T1/20 ,  G06T15/00 ,  G06T17/10

Abstract: A graphics processor that is operable to perform ray tracing is disclosed. When it is determined that a ray intersects a volume represented by a node of a ray tracing acceleration data structure that is associated with a bounding volume primitive, the ray is not tested against the bounding volume primitive to determine whether the ray intersects the bounding volume primitive.

公开(公告)号：US20220114761A1

公开(公告)日：2022-04-14

申请号：US17068738

申请日：2020-10-12

Applicant: Arm Limited

Inventor： Bjorn Fredrik Wictorin, III ,  Jakob Axel Fries

IPC: G06T9/00 ,  G06T3/40 ,  H04N19/60 ,  H04N19/65 ,  H04N19/186

Abstract: Disclosed herein is a method and apparatus for determining decoded data values for a data element of an array of data elements from an encoded representation of the array of data elements, wherein the decoding comprises determining which, if any, bits are missing for the data value(s) for the data element and selecting based on this an adjustment scheme to be applied for the data value(s) for the data element from a plurality of available adjustment schemes. Also disclosed are a method and apparatus for generating an encoding hint comprising an indication of the one or more encoding parameters that were used to generate the encoded representation which encoding hint can then be associated with the decoded data and then used when the decoded data is subsequently to be encoded.

公开(公告)号：US20210011646A1

公开(公告)日：2021-01-14

申请号：US16510200

申请日：2019-07-12

Applicant: Arm Limited

Inventor： Jorn Nystad ,  Edvard Fielding ,  Jakob Axel Fries

IPC: G06F3/06 ,  G06T1/60

Abstract: When storing an array of data in memory, the data array is divided into a plurality of blocks, and for respective groups of the blocks that the data array has been divided into, a set of data representing the group of blocks that includes: for each block of the group of blocks, a set of data for that block of the group of blocks; and a size indication for each of one or more of the blocks of the group of blocks, the size indication for a block of a group of blocks indicating the size in memory of the set of data for that block of the group included in the stored set of data representing the group of blocks, is stored. A set of header data is also stored separately for each group of blocks of the data array.

公开(公告)号：US20200258264A1

公开(公告)日：2020-08-13

申请号：US16739631

申请日：2020-01-10

Applicant: Arm Limited

Inventor： Samuel Martin ,  Jakob Axel Fries ,  Ozgur Ozkurt

IPC: G06T9/40 ,  G09G5/36

Abstract: A data processing system comprises encoding circuitry operable to encode arrays of data elements, decoding circuitry operable to decode encoded versions of arrays of data elements, and consumer circuitry operable to use arrays of data elements. Data indicative of a resolution that is to be used by the consumer circuitry for at least one region of the array of data elements is provided to the encoding circuitry, and the encoding circuitry uses the data indicative of the resolution that is to be used by the consumer circuitry to control the generation of the representation for representing at least one block that the array of data elements is divided into.

公开(公告)号：US10430099B2

公开(公告)日：2019-10-01

申请号：US15472637

申请日：2017-03-29

Applicant: ARM Limited

Inventor： Quinn Carter ,  Lars Oskar Flordal ,  Jakob Axel Fries ,  Andreas Due Engh-Halstvedt

IPC: G06F3/06 ,  G09G5/393 ,  G06T1/20 ,  G06T1/60 ,  G06T11/40

Abstract: A data array to be stored is first divided into a plurality of blocks. Each block is further sub-divided into a set of sub-blocks.Data representing sub-blocks of the data array is stored, together with a header data block for each block that the data array has been divided into.For each block, it is determined whether all the data positions for the block have the same data value associated with them, and, if so, an indication that all of the data positions within the block have the same data value associated with them, and an indication of the same data value that is associated with each of the data positions in the block, is stored in the header data block for that block of the data array.

公开(公告)号：US20180004443A1

公开(公告)日：2018-01-04

申请号：US15636524

申请日：2017-06-28

Applicant: ARM Limited

Inventor： Quinn Carter ,  Lars Oskar Flordal ,  Jakob Axel Fries

IPC: G06F3/06

Abstract: A method of storing encoded blocks of data in memory comprises generating headers for the encoded blocks of data. The headers are stored in memory according to a tiled layout based on tiles of plural adjacent blocks of data elements of the array of data elements. Respective sets of the encoded blocks of data are also stored in respective distinct regions of memory locations that have been allocated to those sets. The method provides an efficient way to access headers and corresponding encoded blocks of data in memory.

公开(公告)号：US20170352165A1

公开(公告)日：2017-12-07

申请号：US15610016

申请日：2017-05-31

Applicant: ARM Limited

Inventor： Lars Oskar Flordal ,  Jakob Axel Fries ,  Toni Viki Brkic

IPC: G06T9/40 ,  H04N19/176 ,  H04N19/186 ,  G06T15/00 ,  H04N19/11 ,  H04N19/96 ,  H04N19/182

CPC classification number: G06T9/40 ,  G06T9/00 ,  G06T15/005 ,  G09G5/39 ,  G09G2340/02 ,  G09G2350/00 ,  G09G2360/12 ,  H04N19/11 ,  H04N19/15 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186 ,  H04N19/96

Abstract: A method of encoding a block of an array of data elements comprises selectively writing out an encoded version of the block either that is encoded using a first encoding scheme, which provides encoded blocks of non-fixed data size, or that is encoded using a second encoding scheme, which provides encoded blocks of fixed data size. The selection of which version of the encoded block to write out is based on the size of the encoded block when encoded using the first encoding scheme. This provides the potential for the encoded block that is written out to be compressed in a more superior manner using the first encoding scheme where possible, whilst also providing an encoded block that has a predictable maximum compressed size.