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公开(公告)号：US12223010B2
公开(公告)日：2025-02-11
申请号：US17339895
申请日：2021-06-04
Applicant: Arm Limited
Inventor： Supreet Jeloka , Mudit Bhargava , Saurabh Pijuskumar Sinha , Rahul Mathur
Abstract: According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.
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公开(公告)号：US11682432B2
公开(公告)日：2023-06-20
申请号：US17343829
申请日：2021-06-10
Applicant: Arm Limited
Inventor： Supreet Jeloka , Saurabh Pijuskumar Sinha , Shidhartha Das , Mudit Bhargava , Rahul Mathur
Abstract: Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.
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公开(公告)号：US20220199125A1
公开(公告)日：2022-06-23
申请号：US17343829
申请日：2021-06-10
Applicant: Arm Limited
Inventor： Supreet Jeloka , Saurabh Pijuskumar Sinha , Shidhartha Das , Mudit Bhargava , Rahul Mathur
Abstract: Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.
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公开(公告)号：US20220130816A1
公开(公告)日：2022-04-28
申请号：US17077532
申请日：2020-10-22
Applicant: Arm Limited
Inventor： Rahul Mathur , Xiaoqing Xu , Andy Wangkun Chen , Mudit Bhargava , Brian Tracy Cline , Saurabh Pijuskumar Sinha
IPC: H01L27/02 , H01L25/065 , H01L23/535 , H01L21/768 , H01L25/00 , G06F30/31
Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.
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公开(公告)号：US10896707B2
公开(公告)日：2021-01-19
申请号：US16290822
申请日：2019-03-01
Applicant: Arm Limited
Inventor： Andy Wangkun Chen , Rahul Mathur , Cyrille Nicolas Dray , Yann Sarrazin , Julien Vincent Poitrat , Yannis Jallamion-Grive , Pranay Prabhat , James Edward Myers , Graham Peter Knight , Jonas {hacek over (S)}vedas
Abstract: Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.
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Patent Agency Ranking
公开(公告)号：US12068025B2
公开(公告)日：2024-08-20
申请号：US17856928
申请日：2022-07-01
Applicant: Arm Limited
Inventor： Rahul Mathur , Edward Martin McCombs, Jr. , Hsin-Yu Chen
IPC: G11C11/00 , G11C11/412 , G11C11/418
CPC classification number: G11C11/418 , G11C11/412
Abstract: Various implementations described herein are directed to a device having memory with banks of bitcells with each bank having a bitcell array. The device may have header circuitry that powers-up a selected bank and powers-down unselected banks during a wake-up mode of operation. In some instances, only the selected bank of the memory is powered-up with the header circuitry during the wake-up mode of operation.
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公开(公告)号：US20240005983A1
公开(公告)日：2024-01-04
申请号：US17856928
申请日：2022-07-01
Applicant: Arm Limited
Inventor： Rahul Mathur , Edward Martin McCombs, JR. , Hsin-Yu Chen
IPC: G11C11/418 , G11C11/412
CPC classification number: G11C11/418 , G11C11/412
Abstract: Various implementations described herein are directed to a device having memory with banks of bitcells with each bank having a bitcell array. The device may have header circuitry that powers-up a selected bank and powers-down unselected banks during a wake-up mode of operation. In some instances, only the selected bank of the memory is powered-up with the header circuitry during the wake-up mode of operation.
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公开(公告)号：US20230402092A1
公开(公告)日：2023-12-14
申请号：US17835912
申请日：2022-06-08
Applicant: Arm Limited
Inventor： Rahul Mathur , Hsin-Yu Chen , Phani Raja Bhushan Chalasani , Kyung Woo Kim , Edward Martin McCombs, JR.
IPC: G11C11/419 , G11C11/412
CPC classification number: G11C11/419 , G11C11/412
Abstract: Various implementations described herein are directed to a device having memory circuitry with bitlines coupled to an array of bitcells. The device may include precharge circuitry that precharges the bitlines during modes of operation including a standby mode of operation and an active mode of operation. In some instances, the precharge circuitry may include a low power mode of operation that prevents precharge of the bitlines during the standby mode of operation.
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公开(公告)号：US11670363B2
公开(公告)日：2023-06-06
申请号：US17238683
申请日：2021-04-23
Applicant: Arm Limited
Inventor： Rahul Mathur , Mudit Bhargava , Andy Wangkun Chen
IPC: G11C5/06 , G11C11/4093 , G11C11/4094 , G11C11/408
CPC classification number: G11C11/4093 , G11C5/06 , G11C11/4085 , G11C11/4094
Abstract: Various implementations described herein are directed to a device having a multi-tiered memory structure with a first tier and a second tier arranged vertically in a stacked configuration. The device may have multiple transistors disposed in the multi-tiered memory structure with first transistors disposed in the first tier and second transistors disposed in the second tier. The device may have a single interconnect that vertically couples the first transistors in the first tier to the second transistors in the second tier.
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公开(公告)号：US11569219B2
公开(公告)日：2023-01-31
申请号：US17077532
申请日：2020-10-22
Applicant: Arm Limited
Inventor： Rahul Mathur , Xiaoqing Xu , Andy Wangkun Chen , Mudit Bhargava , Brian Tracy Cline , Saurabh Pijuskumar Sinha
IPC: H01L27/02 , G06F30/31 , H01L21/768 , H01L23/535 , H01L25/065 , H01L25/00
Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.
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