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    Method, system and circuit for multi-die timing signal distribution
    13.
    发明授权
    Method, system and circuit for multi-die timing signal distribution 有权

    公开(公告)号：US11228316B2

    公开(公告)日：2022-01-18

    申请号：US16522461

    申请日：2019-07-25

    Applicant: Arm Limited

    Inventor： Xiaoqing Xu ,  Saurabh Pijuskumar Sinha ,  Sheng-En Hung ,  Chien-Ju Chao

    IPC: G05F1/04 ,  H03K3/00 ,  H03L7/08 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12

    Abstract: Disclosed are methods, systems and devices for distribution of a timing signal among operational nodes of a circuit device comprising one or more circuit dies. In one implementation, a timing signal distribution network may transmit a timing signal to one or more operational circuit nodes formed on a circuit die and a clock circuit may generate a first clock signal for transmission as the timing signal to the one or more operational circuit nodes. A switch circuit may apply a second clock signal for transmission as the timing signal in lieu of the first clock signal if the circuit die is integrated at least one of the one or more other circuit dies. In another implementation, timing signals received at timing signal terminals of at least two of two or more of operational circuit nodes may be synchronized independently of the timing signal distribution network.

    METHOD, SYSTEM AND CIRCUIT FOR MULTI-DIE TIMING SIGNAL DISTRIBUTION
    14.
    发明申请
    METHOD, SYSTEM AND CIRCUIT FOR MULTI-DIE TIMING SIGNAL DISTRIBUTION 有权

    公开(公告)号：US20210028788A1

    公开(公告)日：2021-01-28

    申请号：US16522461

    申请日：2019-07-25

    Applicant: Arm Limited

    Inventor： Xiaoqing Xu ,  Saurabh Pijuskumar Sinha ,  Sheng-En Hung ,  Chien-Ju Chao

    IPC: H03L7/08 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12

    Abstract: Disclosed are methods, systems and devices for distribution of a timing signal among operational nodes of a circuit device comprising one or more circuit dies. In one implementation, a timing signal distribution network may transmit a timing signal to one or more operational circuit nodes formed on a circuit die and a clock circuit may generate a first clock signal for transmission as the timing signal to the one or more operational circuit nodes. A switch circuit may apply a second clock signal for transmission as the timing signal in lieu of the first clock signal if the circuit die is integrated at least one of the one or more other circuit dies. In another implementation, timing signals received at timing signal terminals of at least two of two or more of operational circuit nodes may be synchronized independently of the timing signal distribution network.

    Multi-tier co-placement for integrated circuitry
    15.
    发明授权
    Multi-tier co-placement for integrated circuitry 有权

    公开(公告)号：US10599806B2

    公开(公告)日：2020-03-24

    申请号：US15939047

    申请日：2018-03-28

    Applicant: Arm Limited

    Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Stephen Lewis Moore ,  Saurabh Pijuskumar Sinha

    IPC: G06F17/50 ,  H01L27/02 ,  H01L23/522

    Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without the inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without the inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without the inter-tier-connection pairs. The method includes iteratively adjusting a location of the standard cells with or without a location of inter-tier connections so as to converge the location of the standard cells with or without the location of the inter-tier connections to optimized or legal locations.

    TSV coupled integrated circuits and methods
    17.
    发明授权
    TSV coupled integrated circuits and methods 有权

    公开(公告)号：US11569219B2

    公开(公告)日：2023-01-31

    申请号：US17077532

    申请日：2020-10-22

    Applicant: Arm Limited

    Inventor： Rahul Mathur ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha

    IPC: H01L27/02 ,  G06F30/31 ,  H01L21/768 ,  H01L23/535 ,  H01L25/065 ,  H01L25/00

    Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

    Methods and Apparatuses for Concurrent Coupling of Inter-Tier Connections
    18.
    发明申请
    Methods and Apparatuses for Concurrent Coupling of Inter-Tier Connections 有权

    公开(公告)号：US20220164513A1

    公开(公告)日：2022-05-26

    申请号：US17103251

    申请日：2020-11-24

    Applicant: Arm Limited

    Inventor： Chien-Ju Chao ,  Pranavi Chandupatla ,  Saurabh Pijuskumar Sinha ,  Sheng-En Hung ,  Xiaoqing Xu

    IPC: G06F30/392 ,  H01L25/065 ,  G06F30/3947

    Abstract: According to one implementation of the present disclosure, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing respective inter-tier connections coupling for first and second networks concurrently on the generated 3D circuit design. The first networks may include power or ground networks, while the second networks may include signal networks. In another implementation, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing inter-tier connections on the generated 3D circuit design during one of a placement stage, a partitioning stage, a clock tree synthesis (CTS) stage, or a routing stage of a physical circuit design procedure.

    METHOD AND APPARATUS FOR POWER MEASUREMENT IN ELECTRONIC CIRCUIT DESIGN AND ANALYSIS
    19.
    发明申请
    METHOD AND APPARATUS FOR POWER MEASUREMENT IN ELECTRONIC CIRCUIT DESIGN AND ANALYSIS 有权

    公开(公告)号：US20220164511A1

    公开(公告)日：2022-05-26

    申请号：US17218670

    申请日：2021-03-31

    Applicant: Arm Limited

    Inventor： Xiaoqing Xu ,  Zhiyao Xie ,  Shidhartha Das ,  Matthew James Walker ,  Kumara Guru Palaniswamy ,  Matthew Paul Elwood

    IPC: G06F30/367 ,  G01R21/133 ,  G01R31/317

    Abstract: A power meter for measuring power usage in a circuit includes preprocessor and a weighting network. The pre-processor is configured to receive toggle data for a number of power proxy signals in the circuit for a plurality of clock cycles of the circuit in a first time window. The power proxy signals and weighting values are determined automatically from simulated or emulated toggle data. For each power proxy signal, the pre-processor averages the toggle data over one or more clock cycles in one or more second time windows, within the first time window, to provide averaged toggle data, and outputs the averaged toggle data for each second time window. The weighting network is configured to combine the averaged toggle data from the power proxy signals, based on a set of weight values, to provide a measure of the power usage.

    DIELET DESIGN TECHNIQUES
    20.
    发明申请
    DIELET DESIGN TECHNIQUES 有权

    公开(公告)号：US20210081508A1

    公开(公告)日：2021-03-18

    申请号：US16569482

    申请日：2019-09-12

    Applicant: Arm Limited

    Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha ,  Stephen Lewis Moore ,  Mudit Bhargava

    IPC: G06F17/50

    Abstract: Various implementations described herein are directed to an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) may include multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.

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