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公开(公告)号：US11748186B2
公开(公告)日：2023-09-05
申请号：US17712380
申请日：2022-04-04
Applicant: Advanced Micro Devices, Inc.
Inventor： Andrew G. Kegel , David A. Roberts
CPC classification number: G06F11/076 , G06F11/0706 , G06F11/0793 , G06N3/02 , G06N5/04 , G06V10/764 , G06V10/82 , G06N20/00
Abstract: A neural network runs a known input data set using an error free power setting and using an error prone power setting. The differences in the outputs of the neural network using the two different power settings determine a high level error rate associated with the output of the neural network using the error prone power setting. If the high level error rate is excessive, the error prone power setting is adjusted to reduce errors by changing voltage and/or clock frequency utilized by the neural network system. If the high level error rate is within bounds, the error prone power setting can remain allowing the neural network to operate with an acceptable error tolerance and improved efficiency. The error tolerance can be specified by the neural network application.
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公开(公告)号：US20210334012A1
公开(公告)日：2021-10-28
申请号：US17368461
申请日：2021-07-06
Applicant: Advanced Micro Devices, Inc.
Inventor： Andrew G. Kegel , Steven E. Raasch
IPC: G06F3/06 , G06F16/907 , G06F12/0891
Abstract: An electronic device includes a non-volatile memory and a memory controller. The memory controller selects, from the type-duration table, a duration for which data of a type of data is to be stored in a non-volatile memory. The memory controller writes the data to the non-volatile memory using values of one or more write parameters selected by the memory controller based on the duration. The memory controller sets an expected lifetime value in a record for the data in the expected lifetime table to indicate an expected lifetime of the data in the non-volatile memory.
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公开(公告)号：US10678702B2
公开(公告)日：2020-06-09
申请号：US15167038
申请日：2016-05-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov , Andrew G. Kegel
IPC: G06F12/10 , G06F12/1009 , G06F12/1081 , G06F12/1027 , G06F3/06
Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.
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公开(公告)号：US10282308B2
公开(公告)日：2019-05-07
申请号：US15191462
申请日：2016-06-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Nuwan Jayasena , Andrew G. Kegel
IPC: G06F12/10 , G06F12/1027 , G06F12/1009
Abstract: A method and apparatus for reducing TLB shootdown operation overheads in accelerator-based computing systems is described. The disclosed method and apparatus may also be used in the areas of near-memory and in-memory computing, where near-memory or in-memory compute units may need to share a host CPU's virtual address space. Metadata is associated with page table entries (PTEs) and mechanisms use the metadata to limit the number of processing elements that participate in a TLB shootdown operation.
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公开(公告)号：US20190042313A1
公开(公告)日：2019-02-07
申请号：US15974014
申请日：2018-05-08
Applicant: Advanced Micro Devices, Inc.
Inventor： Andrew G. Kegel , David A. Roberts
Abstract: Systems, apparatuses, and methods for sharing an field programmable gate array compute engine are disclosed. A system includes one or more processors and one or more FPGAs. The system receives a request, generated by a first user process, to allocate a portion of processing resources on a first FPGA. The system maps the portion of processing resources of the first FPGA into an address space of the first user process. The system prevents other user processes from accessing the portion of processing resources of the first FPGA. Later, the system detects a release of the portion of the processing resources on the first FPGA by the first user process. Then, the system receives a second request to allocate the first FPGA from a second user process. In response to the second request, the system maps the first FPGA into an address space of the second user process.
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Patent Agency Ranking
公开(公告)号：US10164639B1
公开(公告)日：2018-12-25
申请号：US15812411
申请日：2017-11-14
Applicant: Advanced Micro Devices, Inc.
Inventor： David A. Roberts , Andrew G. Kegel , Elliot H. Mednick
IPC: H03K19/177 , G06F17/50 , G06F15/78
Abstract: A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.
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公开(公告)号：US20170344490A1
公开(公告)日：2017-11-30
申请号：US15167038
申请日：2016-05-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov , Andrew G. Kegel
IPC: G06F12/1009 , G06F3/06
Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.
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公开(公告)号：US09396110B2
公开(公告)日：2016-07-19
申请号：US13725177
申请日：2012-12-21
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Andrew G. Kegel
CPC classification number: G06F12/0638 , G06F3/0679 , G06F11/0751 , G06F11/2015 , G06F12/0804 , G06F12/0866
Abstract: Memory units and computer systems are provided. The computer systems include a memory unit. The memory unit includes a stable storage unit, an unstable storage unit, and a controller. The unstable storage unit stores pending write operations for the stable storage unit. The controller is configured to determine the locations in the unstable storage that store the pending write information and to selectively write the pending write operations to the stable storage unit when power to the memory unit is interrupted.
Abstract translation: 提供内存单元和计算机系统。 计算机系统包括存储单元。 存储单元包括稳定存储单元，不稳定存储单元和控制器。 不稳定存储单元存储稳定存储单元的待处理写入操作。 控制器被配置为确定存储未决写入信息的不稳定存储器中的位置，并且当对存储器单元的电力中断时，有选择地将待决写入操作写入稳定存储单元。
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公开(公告)号：US20150355883A1
公开(公告)日：2015-12-10
申请号：US14296373
申请日：2014-06-04
Applicant: Advanced Micro Devices, Inc.
Inventor： Andrew G. Kegel
CPC classification number: G06F5/085 , G06F5/065 , G06F5/10 , G06F2205/063 , G06F2205/064
Abstract: The described embodiments include a computing device with a queue stored in a memory of the computing device. In the described embodiments, the queue may be relocated and/or resized in the memory using a queue address, a queue size, a head pointer, and/or a tail pointer associated with the queue. In some embodiments, a processor, at the request of a software entity, updates one or more values associated with the queue to relocate and/or resize the queue. In response, a write mechanism performs one or more operations to enable the use of the relocated and/or resized queue. In addition, in some embodiments, the processor, at the request of the software entity, performs one or more operations to process remaining valid entries in an original location of the queue after the queue has been relocated.
Abstract translation: 所描述的实施例包括具有存储在计算设备的存储器中的队列的计算设备。 在所描述的实施例中，可以使用与队列相关联的队列地址，队列大小，头部指针和/或尾部指针，将队列重新定位和/或调整大小在存储器中。 在一些实施例中，处理器在软件实体的请求下更新与队列相关联的一个或多个值以重新定位和/或调整队列大小。 作为响应，写入机制执行一个或多个操作以使得能够使用重定位和/或调整大小的队列。 此外，在一些实施例中，处理器在软件实体的请求下执行一个或多个操作以在队列被重定位之后处理队列的原始位置中的剩余有效条目。
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公开(公告)号：US11956368B2
公开(公告)日：2024-04-09
申请号：US17555020
申请日：2021-12-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov , Andrew G. Kegel
CPC classification number: H04L9/3239 , G06N3/08
Abstract: An approach is provided for implementing a useful proof-of-work consensus algorithm. A proposed block is received. A combined hash value is generated based on the proposed block and a nonce value. The combined hash value is divided into a plurality of hash value pieces that each correspond to a work packet of a plurality of work packets. One or more requests are transmitted for the plurality of work packets that correspond to the plurality of hash value pieces. In response to receiving the plurality of work packets, a plurality of results is generated by performing, for each work packet of the plurality of work packets, one or more operations to complete work specified by the respective work packet. In response to determining that at least one result of the plurality of results satisfies one or more criteria, the proposed block is added to a blockchain maintained by the blockchain network.
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