公开(公告)号：US11714559B2

公开(公告)日：2023-08-01

申请号：US17033170

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. LeBeane ,  Khaled Hamidouche ,  Hari S. Thangirala ,  Brandon Keith Potter

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0802

CPC classification number: G06F3/0619 ,  G06F3/067 ,  G06F3/0656 ,  G06F12/0223 ,  G06F12/0802 ,  G06F2212/152

Abstract: A framework disclosed herein extends a relaxed, scoped memory model to a system that includes nodes across a commodity network and maintains coherency across the system. A new scope, cluster scope, is defined, that allows for memory accesses at scopes less than cluster scope to operate on locally cached versions of remote data from across the commodity network without having to issue expensive network operations. Cluster scope operations generate network commands that are used to synchronize memory across the commodity network.

公开(公告)号：US11687460B2

公开(公告)日：2023-06-27

申请号：US15498076

申请日：2017-04-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. LeBeane ,  Walter B. Benton ,  Vinay Agarwala

IPC: G06F12/0817 ,  G06F12/1081 ,  G06F12/0831 ,  G06F12/0813 ,  G06F13/28

CPC classification number: G06F12/0828 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/1081 ,  G06F13/28 ,  G06F2212/1021 ,  G06F2212/154 ,  G06F2212/621 ,  G06F2212/622

Abstract: Methods, devices, and systems for GPU cache injection. A GPU compute node includes a network interface controller (NIC) which includes NIC receiver circuitry which can receive data for processing on the GPU, NIC transmitter circuitry which can send the data to a main memory of the GPU compute node and which can send coherence information to a coherence directory of the GPU compute node based on the data. The GPU compute node also includes a GPU which includes GPU receiver circuitry which can receive the coherence information; GPU processing circuitry which can determine, based on the coherence information, whether the data satisfies a heuristic; and GPU loading circuitry which can load the data into a cache of the GPU from the main memory if on the data satisfies the heuristic.

公开(公告)号：US11321241B2

公开(公告)日：2022-05-03

申请号：US17008435

申请日：2020-08-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  Michael W. LeBeane

IPC: G06F12/1027 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/126 ,  G06F12/0846

Abstract: Techniques are disclosed for processing address translations. The techniques include detecting a first miss for a first address translation request for a first address translation in a first translation lookaside buffer, in response to the first miss, fetching the first address translation into the first translation lookaside buffer and evicting a second address translation from the translation lookaside buffer into an instruction cache or local data share memory, detecting a second miss for a second address translation request referencing the second address translation, in the first translation lookaside buffer, and in response to the second miss, fetching the second address translation from the instruction cache or the local data share memory.

公开(公告)号：US10963309B2

公开(公告)日：2021-03-30

申请号：US15267936

申请日：2016-09-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. LeBeane ,  Abhisek Pan ,  Steven K. Reinhardt

IPC: G06F9/48 ,  G06F9/50

Abstract: Techniques for scheduling processing tasks in a device having multiple computing elements are disclosed. A network interface controller of the device receives processing tasks, for execution on the computing elements, from a network that is external to the device. The network interface controller schedules the tasks for execution on the computing devices based on policy data available to the network interface controller. A scheduler within the network interface controller, which can be implemented as a standalone processing unit (such as a microcontroller, a programmable processing core, or an application specific integrated circuit), performs such scheduling, thereby freeing the central processing unit of the device from the burden of performing scheduling operations. The scheduler schedules the tasks according to any technically feasible scheduling technique.

公开(公告)号：US10936697B2

公开(公告)日：2021-03-02

申请号：US16044145

申请日：2018-07-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Khaled Hamidouche ,  Michael W. LeBeane ,  Nicholas P. Malaya ,  Joseph L. Greathouse

IPC: G06F17/16 ,  G06F9/38 ,  G06F9/30 ,  G06F17/12

Abstract: A method includes storing a first portion of a sparse triangular matrix in a local memory and launching a kernel for executing a set of workgroups. The first portion includes a plurality of row blocks, and each workgroup in the set of workgroups is associated with one of the plurality of row blocks. The method also includes, for each workgroup in the set of workgroups, solving the row block. The row block is solved by, for each row segment of a first subset of row segments in the row block, calculating a partial sum for the row segment based on one or more matrix elements in the row segment, and writing the partial sum to a remote memory of a first remote processing unit prior to terminating the kernel.

公开(公告)号：US20200034405A1

公开(公告)日：2020-01-30

申请号：US16044145

申请日：2018-07-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Khaled Hamidouche ,  Michael W. LeBeane ,  Nicholas P. Malaya ,  Joseph L. Greathouse

IPC: G06F17/16 ,  G06F9/38 ,  G06F17/12 ,  G06F9/30

Abstract: A method includes storing a first portion of a sparse triangular matrix in a local memory and launching a kernel for executing a set of workgroups. The first portion includes a plurality of row blocks, and each workgroup in the set of workgroups is associated with one of the plurality of row blocks. The method also includes, for each workgroup in the set of workgroups, solving the row block. The row block is solved by, for each row segment of a first subset of row segments in the row block, calculating a partial sum for the row segment based on one or more matrix elements in the row segment, and writing the partial sum to a remote memory of a first remote processing unit prior to terminating the kernel.

公开(公告)号：US20180107627A1

公开(公告)日：2018-04-19

申请号：US15297079

申请日：2016-10-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. LeBeane ,  Steven K. Reinhardt

IPC: G06F15/173 ,  H04L12/863

CPC classification number: G06F15/17331 ,  H04L47/50 ,  H04L49/9063

Abstract: Methods, devices, and systems for transmitting data over a computer communications network are disclosed. A queue of communications commands can be pre-generated using a central processing unit (CPU) and stored in a device memory of a network interface controller (NIC). Thereafter, if a graphics processing unit (GPU) has data to communicate to a remote GPU, it can store the data in a send buffer, where the location in the buffer is pointed to by a pre-generated command. The GPU can then signal to the interface device that the data is ready, triggering execution of the pre-generated command to send the data.

公开(公告)号：US20170083382A1

公开(公告)日：2017-03-23

申请号：US14862038

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. LeBeane ,  Deepak Majeti ,  Mauricio Breternitz

IPC: G06F9/50 ,  G06F1/32 ,  G06F9/48

CPC classification number: G06F9/5094 ,  G06F1/206 ,  G06F1/3243 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/4856 ,  G06F9/4893 ,  Y02D10/152 ,  Y02D10/16 ,  Y02D10/24

Abstract: First and second processor cores are configured to concurrently execute tasks. A scheduler is configured to schedule tasks for execution by the first and second processor cores. The first processor core is configured to selectively steal a task that was previously scheduled for execution by the second processor core based on additional power consumption incurred by migrating the task from the second processor core to the first processor core.