公开(公告)号：US20240329839A1

公开(公告)日：2024-10-03

申请号：US18190724

申请日：2023-03-27

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Tsun-Ho Liu ,  Anwar Parvez Kashem ,  Pouya Najafi Ashtiani ,  Gershom Birk ,  David Da Wei Lin

IPC: G06F3/06 ,  G06F1/08 ,  H04L7/00

CPC classification number: G06F3/0611 ,  G06F1/08 ,  G06F3/0656 ,  G06F3/0673 ,  H04L7/0016

Abstract: Clock domain phase adjustment techniques and systems for memory operations are described. In one example, a physical memory is communicatively coupled to a physical layer via a first clock domain and a memory controller is communicatively coupled to the physical layer via a second clock domain that is different than the first clock domain. A buffer is implemented in the physical layer. The buffer is configured to set a phase adjustment for a latency setting between the first and second clock domains. The phase adjustment is based on whether a mismatch has occurred in data output by the buffer to the memory controller based on a comparison to the latency setting.

公开(公告)号：US11989050B2

公开(公告)日：2024-05-21

申请号：US17565382

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani ,  Deepesh John

IPC: G06F1/08 ,  H03K5/22 ,  H03K5/00

CPC classification number: G06F1/08 ,  H03K5/22 ,  H03K2005/00286

Abstract: Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.

公开(公告)号：US20230409232A1

公开(公告)日：2023-12-21

申请号：US17845922

申请日：2022-06-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani ,  Tsun Ho Liu

IPC: G06F3/06 ,  G06K9/62

CPC classification number: G06F3/0656 ,  G06K9/6256 ,  G06F3/0683 ,  G06F3/0604

Abstract: A method and apparatus for training data in a computer system includes reading data stored in a first memory address in a memory and writing it to a buffer. Training data is generated for transmission to the first memory address. The data is transmitted to the first memory address. Information relating to the training data is read from the first memory address and the stored data is read from the buffer and written to the memory area where the training data was transmitted.

公开(公告)号：US20230206973A1

公开(公告)日：2023-06-29

申请号：US17564426

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani

IPC: G11C7/22 ,  G11C7/10 ,  G11C5/06

CPC classification number: G11C7/222 ,  G11C5/06 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/1093

Abstract: Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the training of the interface, techniques disclosed comprise generating a training clock from the clock signal at the first pulse rate, the training clock having a clock signal at a second pulse rate, and sending, based on the generated training clock, command signals, including address data, to the DRAM.

公开(公告)号：US20230205252A1

公开(公告)日：2023-06-29

申请号：US17565382

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani ,  Deepesh John

IPC: G06F1/08 ,  H03K5/22

CPC classification number: G06F1/08 ,  H03K5/22 ,  H03K2005/00286

Abstract: Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.