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公开(公告)号：US20230208424A1
公开(公告)日：2023-06-29
申请号：US17563980
申请日：2021-12-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Nur Mohammad Baksh , Deepesh John
IPC: H03K19/096 , H03K19/0185 , H03K3/012
CPC classification number: H03K19/0963 , H03K19/018521 , H03K3/012
Abstract: Systems, apparatuses, and methods for implementing a low-power single-phase logic gate latch for clock-gating are disclosed. A latch circuit includes shared clocked transistors without including clock inverters. The shared clocked transistors include a P-type clocked transistor and an N-type clocked transistor, with the clock input coupled to the gate of the P-type clocked transistor and to the gate of the N-type clocked transistor. The P-type clocked transistor is coupled between first and second transistor stacks of the latch. The N-type clocked transistor is coupled to a source gate of a first stack N-type transistor gated by a data input and to a source gate of a second stack N-type transistor gated by the inverted data input. The latch has a lower clock pin capacitance than a traditional logic gate latch while also avoiding having clock inverters which reduces dynamic power consumption.
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公开(公告)号：US20240295898A1
公开(公告)日：2024-09-05
申请号：US18663864
申请日：2024-05-14
Applicant: Advanced Micro Devices, Inc.
Inventor： Anwar Kashem , Craig Daniel Eaton , Pouya Najafi Ashtiani , Deepesh John
CPC classification number: G06F1/08 , H03K5/22 , H03K2005/00286
Abstract: Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.
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公开(公告)号：US11989050B2
公开(公告)日：2024-05-21
申请号：US17565382
申请日：2021-12-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Anwar Kashem , Craig Daniel Eaton , Pouya Najafi Ashtiani , Deepesh John
CPC classification number: G06F1/08 , H03K5/22 , H03K2005/00286
Abstract: Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.
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公开(公告)号：US20230205252A1
公开(公告)日：2023-06-29
申请号：US17565382
申请日：2021-12-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Anwar Kashem , Craig Daniel Eaton , Pouya Najafi Ashtiani , Deepesh John
CPC classification number: G06F1/08 , H03K5/22 , H03K2005/00286
Abstract: Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.
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公开(公告)号：US12160238B2
公开(公告)日：2024-12-03
申请号：US17563980
申请日：2021-12-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Nur Mohammad Baksh , Deepesh John
IPC: H03K19/096 , H03K3/012 , H03K19/0185
Abstract: Systems, apparatuses, and methods for implementing a low-power single-phase logic gate latch for clock-gating are disclosed. A latch circuit includes shared clocked transistors without including clock inverters. The shared clocked transistors include a P-type clocked transistor and an N-type clocked transistor, with the clock input coupled to the gate of the P-type clocked transistor and to the gate of the N-type clocked transistor. The P-type clocked transistor is coupled between first and second transistor stacks of the latch. The N-type clocked transistor is coupled to a source gate of a first stack N-type transistor gated by a data input and to a source gate of a second stack N-type transistor gated by the inverted data input. The latch has a lower clock pin capacitance than a traditional logic gate latch while also avoiding having clock inverters which reduces dynamic power consumption.
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Patent Agency Ranking
公开(公告)号：US10303200B2
公开(公告)日：2019-05-28
申请号：US15441613
申请日：2017-02-24
Applicant: Advanced Micro Devices, Inc.
Inventor： Deepesh John , Steven Kommrusch , Vibhor Mittal
IPC: G06F1/32 , G06F1/08 , G06F1/3203
Abstract: A method for implementing clock dividers includes providing, in response to detecting a voltage drop at a processor core, an input clock signal to a transmission gate multiplexer for selecting between one of two stretch-enable signals. In some embodiments, selecting between the one of two stretch-enable signals includes inputting a set of core clock enable signals into a clock divider circuit, and modifying the set of core clock enable signals to generate the stretch-enable signals. An output clock signal is generated based on the selected stretch-enable signal.
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公开(公告)号：US11967960B2
公开(公告)日：2024-04-23
申请号：US17389749
申请日：2021-07-30
Applicant: Advanced Micro Devices, Inc.
Inventor： David M. Dahle , Richard Martin Born , Deepesh John
CPC classification number: H03L7/0814 , G06F5/08 , H03L7/087 , H03L7/195 , G06F2205/061
Abstract: Methods and apparatus for synchronizing data transfers across clock domains for using heads-up indications. An integrated circuit includes a first-in first-out buffer (FIFO); a memory controller configured to operate in a first clock domain and coupled to the FIFO, the first clock domain associated with a first clock signal; a data fabric configured to operate in a second clock domain and coupled to the FIFO, the second clock domain associated with a second clock signal, a second frequency of the second clock signal being different from a first frequency of the first clock signal; and a controller coupled to the FIFO. In some instances, the controller determines a phase relationship between the first clock signal and the second clock signal; monitors one or more first clock edges of the first clock signal and one or more second clock edges of the second clock signal; and sends a first heads-up signal to the memory controller.
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公开(公告)号：US20230035110A1
公开(公告)日：2023-02-02
申请号：US17389749
申请日：2021-07-30
Applicant: Advanced Micro Devices, Inc.
Inventor： David M. Dahle , Richard Martin Born , Deepesh John
Abstract: Methods and apparatus for synchronizing data transfers across clock domains for using heads-up indications. An integrated circuit includes a first-in first-out buffer (FIFO); a memory controller configured to operate in a first clock domain and coupled to the FIFO, the first clock domain associated with a first clock signal; a data fabric configured to operate in a second clock domain and coupled to the FIFO, the second clock domain associated with a second clock signal, a second frequency of the second clock signal being different from a first frequency of the first clock signal; and a controller coupled to the FIFO. In some instances, the controller determines a phase relationship between the first clock signal and the second clock signal; monitors one or more first clock edges of the first clock signal and one or more second clock edges of the second clock signal; and sends a first heads-up signal to the memory controller.
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公开(公告)号：US10924120B1
公开(公告)日：2021-02-16
申请号：US16696285
申请日：2019-11-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Deepesh John , Samiul Haque Khan , Vibhor Mittal , Shravan Lakshman , Teja Singh
Abstract: An oscillator circuit includes a phase-locked loop (PLL) with a plurality of voltage controlled oscillator (VCO), a clock divider circuit receiving the VCO phase outputs and outputting a first stage clock signal with an adjustable clock period related to the PLL period based on selecting a combination of two of the VCO phase outputs. The first stage clock signal has a balanced duty cycle at frequencies that are related to the PLL frequency by even fractional divisions of the VCO phase output period based on the quantity VCO phase outputs, and an unbalanced duty cycle at frequencies that are related by odd fractional divisions. A duty cycle adjustment (DCA) circuit receives the first stage clock signal selectively adjusts a falling edge of the first stage clock signal to provide an even duty cycle and feeds a resulting signal to the second stage clock signal output.
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公开(公告)号：US08947124B2
公开(公告)日：2015-02-03
申请号：US14178477
申请日：2014-02-12
Applicant: Advanced Micro Devices, Inc.
Inventor： Deepesh John , Teja Singh , Sundar Rangarajan
IPC: H03K19/0175
CPC classification number: H03K19/0175
Abstract: An integrated circuit device comprising first circuitry including first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry comprising second logic devices, a first clock gater and a second clock gater. The first and second clock gaters comprise a programmable delay circuit.
Abstract translation: 一种集成电路装置，包括第一电路，其包括用于将时钟信号分配给第一逻辑装置的第一逻辑装置和时钟树，以及包括第二逻辑装置的第二电路，第一时钟门控器和第二时钟门控器。 第一和第二时钟加法器包括可编程延迟电路。
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