公开(公告)号：US20220367384A1

公开(公告)日：2022-11-17

申请号：US17321139

申请日：2021-05-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl APPELT ,  Kay Stefan ESSIG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L23/433

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate, a semiconductor device, an encapsulant, a balance structure, and a warpage-resistant layer. The semiconductor device is disposed on the substrate. The encapsulant encapsulates the semiconductor device. The balance structure is on the semiconductor device and contacting the encapsulant. The warpage-resistant layer is between the semiconductor device and the balance structure. The encapsulant contacts a lateral surface of the warpage-resistant layer.

公开(公告)号：US20220336332A1

公开(公告)日：2022-10-20

申请号：US17233294

申请日：2021-04-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl APPELT

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/053 ,  H01L21/48 ,  H01L21/56

Abstract: A conductive structure, a package structure and a method for manufacturing the same are provided. The conductive structure includes a main portion, a first electrical contact, a second electrical contact, a first post and a second post. The main portion has a first surface and a second surface opposite to the first surface. The first electrical contact is disposed adjacent to the first surface of the main portion. The second electrical contact is disposed adjacent to the second surface of the main portion and electrically connected to the first electrical contact. The first post is electrically connected to the first electrical contact. The second post is electrically connected to the second electrical contact.

公开(公告)号：US20220115288A1

公开(公告)日：2022-04-14

申请号：US17066407

申请日：2020-10-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl APPELT ,  Kay Stefan ESSIG

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A substrate structure, a semiconductor package structure including the same and a method for manufacturing the same are provided. The substrate structure includes a first passivation layer, a first circuit layer and a first protection layer. The first passivation layer has a first surface and a second surface opposite to the first surface. The first circuit layer has an outer lateral surface. A first portion of the first circuit layer is disposed in the first passivation layer. The first protection layer is disposed on a second portion of the first circuit layer and exposed from the first surface of the first passivation layer. The outer lateral surface of the first circuit layer is covered by the first passivation layer or the first protection layer.

公开(公告)号：US20210118775A1

公开(公告)日：2021-04-22

申请号：US16655178

申请日：2019-10-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl APPELT

IPC: H01L23/495 ,  H01L23/00

Abstract: A leadframe includes a first conductive layer, a plurality of conductive pillars and a first package body. The first conductive layer has a first surface and a second surface opposite to the first surface. The plurality of conductive pillars are disposed on the first surface of the first conductive layer. The first package body is disposed on the first surface of the first conductive layer and covers the conductive pillars. The conductive pillars and the first conductive layer are integratedly formed.

公开(公告)号：US20190006308A1

公开(公告)日：2019-01-03

申请号：US15636339

申请日：2017-06-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bernd Karl APPELT

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56

Abstract: A semiconductor package includes at least one semiconductor element, an encapsulant, a first circuitry, a second circuitry and at least one first stud bump. The encapsulant covers at least a portion of the semiconductor element. The encapsulant has a first surface and a second surface opposite to the first surface. The first circuitry is disposed adjacent to the first surface of the encapsulant. The second circuitry is disposed adjacent to the second surface of the encapsulant. The first stud bump is disposed in the encapsulant, and electrically connects the first circuitry and the second circuitry. The first stud bump contacts the second circuitry directly.

公开(公告)号：US20160218021A1

公开(公告)日：2016-07-28

申请号：US14606138

申请日：2015-01-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bernd Karl APPELT ,  Kay Stefan ESSIG ,  William T. CHEN ,  Yuan-Chang SU

IPC: H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L21/568 ,  H01L21/4832 ,  H01L21/4857 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/13101 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81444 ,  H01L2224/85444 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor package and method of manufacturing the same. The semiconductor package includes a first die, a plurality of conductive pads, a package body and a plurality of first traces. The plurality of conductive pads electrically connect to the first die, and each of the plurality of conductive pads has a lower surface. The package body encapsulates the first die and the plurality of conductive pads and exposes the lower surface of each of the plurality of conductive pads from a lower surface of the package body. The plurality of first traces are disposed on the lower surface of the package body and are connected to the lower surface of each of the plurality of conductive pads. A thickness of each of the plurality of first traces is less than 100 μm.

Abstract translation: 本公开涉及一种半导体封装及其制造方法。 半导体封装包括第一裸片，多个导电焊盘，封装主体和多个第一迹线。 多个导电焊盘电连接到第一管芯，并且多个导电焊盘中的每一个具有下表面。 封装体封装第一管芯和多个导电焊盘，并且从封装体的下表面暴露多个导电焊盘中的每一个的下表面。 多个第一迹线设置在封装主体的下表面上并且连接到多个导电焊盘中的每一个的下表面。 多个第一迹线中的每一个的厚度小于100μm。

公开(公告)号：US20230058358A1

公开(公告)日：2023-02-23

申请号：US17408297

申请日：2021-08-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl APPELT

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

Abstract: An electronic package, a semiconductor package structure and a method for manufacturing the same are provided. The electronic package includes a carrier, a first electronic component, an electrical extension structure, and an encapsulant. The carrier has a first face and a second face opposite to the first face. The first electronic component is adjacent to the first face of the carrier. The electrical extension structure is adjacent to the first face of the carrier and defines a space with the carrier for accommodating the first electronic component, the electrical extension structure is configured to connect the carrier with an external electronic component. The encapsulant encapsulates the first electronic component and at least a portion of the electrical extension structure.

公开(公告)号：US20220328416A1

公开(公告)日：2022-10-13

申请号：US17225832

申请日：2021-04-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl APPELT ,  Kay Stefan ESSIG

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/49 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate and a first passive device. The substrate has a first surface and a second surface opposite to the first surface. The first passive device includes a first terminal and a second terminal, wherein the first terminal is closer to the first surface than to the second surface, and the second terminal is closer to the second surface than to the first surface.

公开(公告)号：US20220115328A1

公开(公告)日：2022-04-14

申请号：US17066408

申请日：2020-10-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl APPELT ,  Kay Stephan ESSIG

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

Abstract: An electronic package and manufacturing method thereof are provided. The electronic package includes a substrate, a first encapsulant, a wettable flank and a shielding layer. The substrate includes a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface. The first encapsulant is disposed on the first surface of the substrate. The wettable flank is exposed from the side surface of the substrate. The shielding layer covers a side surface of the first encapsulant, wherein on the side surface of the substrate, the shielding layer is spaced apart from the wettable flank.

公开(公告)号：US20220115310A1

公开(公告)日：2022-04-14

申请号：US17066411

申请日：2020-10-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl APPELT ,  Kay Stephan ESSIG

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: An electronic package and method for manufacturing the same are provided. The electronic package includes a substrate and a wetting layer. The substrate includes a plurality of conductive step structures each including a first portion and a second portion. The first portion has a first bottom surface, a first outer surface and a first inner surface. The second portion has a second bottom surface, a second outer surface and a second inner surface, wherein the second portion partially exposes the first bottom surface. The wetting layer at least covers the second bottom surface, the second outer surface and the second inner surface of the second portion of each of the conductive step structures.