公开(公告)号：US07598161B2

公开(公告)日：2009-10-06

申请号：US11861534

申请日：2007-09-26

Applicant: Jingrong Zhou ,  Mark Michael ,  Donna Michael, legal representative ,  David Wu ,  James F. Buller ,  Akif Sultan

Inventor： Jingrong Zhou ,  Mark Michael ,  David Wu ,  James F. Buller ,  Akif Sultan

IPC: H01L21/425

CPC classification number: H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1083

Abstract: The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.

Abstract translation: 本文描述的光晕植入技术采用在光晕掺杂剂轰击期间产生晕轮植入物阴影效应的光晕注入掩模。 第一晶体管器件结构和第二晶体管器件结构形成在晶片上，使得它们彼此正交地取向。 创建了常见的光晕注入掩模，其特征在于，在第一晶体管器件结构的扩散区域的晕圈注入期间防止第二晶体管器件结构的扩散区域的光晕注入，并且具有防止第 在第二晶体管器件结构的扩散区的晕圈注入期间的第一晶体管器件结构。 晶体管器件结构的正交取向和光晕注入掩模的图案消除了创建多个注入掩模以实现晶体管器件结构的不同阈值电压的需要。

公开(公告)号：US20090090969A1

公开(公告)日：2009-04-09

申请号：US11867743

申请日：2007-10-05

Applicant: Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

Inventor： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

Abstract translation: 第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。 第一晶体管的电压阈值基于第一偏置电荷。 第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。 第二晶体管的电压阈值基于第二偏置电荷。

公开(公告)号：US06365516B1

公开(公告)日：2002-04-02

申请号：US09483081

申请日：2000-01-14

Applicant: Austin Frenkel ,  Akif Sultan ,  Paul Besser

Inventor： Austin Frenkel ,  Akif Sultan ,  Paul Besser

IPC: H01L2144

CPC classification number: H01L21/0206 ,  H01L21/28518

Abstract: Various methods of fabricating a silicide structure are provided. In one aspect, a method of fabricating a circuit structure on a silicon surface is provided that includes exposing the silicon surface to a plasma ambient containing hydrogen and an inert gas, and depositing a metallic material capable of forming silicide on the silicon surface. The metallic material is heated to form a metal silicide on the silicon surface. The method provides for low sheet resistance silicide structures by eliminating native oxide films without the risk of spacer material backsputtering.

Abstract translation: 提供了制造硅化物结构的各种方法。 一方面，提供一种在硅表面上制造电路结构的方法，其包括将硅表面暴露于含有氢气和惰性气体的等离子体环境中，以及在硅表面上沉积能够形成硅化物的金属材料。 金属材料被加热以在硅表面上形成金属硅化物。 该方法通过消除天然氧化物膜而不会产生间隔材料反溅镀的风险，从而提供低电阻硅化物结构。

公开(公告)号：US06346463B1

公开(公告)日：2002-02-12

申请号：US09565858

申请日：2000-05-05

Applicant: Akif Sultan ,  Frederick N. Hause

Inventor： Akif Sultan ,  Frederick N. Hause

IPC: H01L2104

CPC classification number: H01L29/1079 ,  H01L21/26513 ,  H01L21/823493

Abstract: A method for forming a semiconductor device is provided. A base layer is provided. A first epitaxial layer having a first dopant at a first concentration is formed above the base layer. A second epitaxial layer having a second dopant at a second concentration is formed above the first epitaxial layer. The second concentration is greater than the first concentration. A third epitaxial layer having a third dopant at a third concentration is formed above the second epitaxial layer. The third concentration is less than the second concentration. Ions are implanted in the third epitaxial layer to form an implant region. The implant region is in contact with the second epitaxial layer. A semiconductor device comprises a base layer, first, second, and third epitaxial layers, and an implant region. The first epitaxial layer has a first dopant at a first concentration disposed above the base layer. The second epitaxial layer has a second dopant at a second concentration disposed above the first epitaxial layer. The second concentration is greater than the first concentration. The third epitaxial layer has a third dopant at a third concentration disposed above the second epitaxial layer. The third concentration is less than the second concentration. The implant region is defined in the third epitaxial layer and is in contact with the second epitaxial layer.

Abstract translation: 提供一种形成半导体器件的方法。 提供基层。 具有第一浓度的第一掺杂剂的第一外延层形成在基层之上。 具有第二浓度的第二掺杂剂的第二外延层形成在第一外延层的上方。 第二浓度大于第一浓度。 具有第三浓度的第三掺杂剂的第三外延层形成在第二外延层的上方。 第三浓度小于第二浓度。 将离子注入第三外延层以形成植入区。 注入区域与第二外延层接触。 半导体器件包括基极层，第一，第二和第三外延层以及植入区域。 第一外延层具有设置在基极层之上的第一浓度的第一掺杂剂。 第二外延层具有设置在第一外延层上方的第二浓度的第二掺杂剂。 第二浓度大于第一浓度。 第三外延层具有设置在第二外延层上方的第三浓度的第三掺杂剂。 第三浓度小于第二浓度。 注入区域限定在第三外延层中并且与第二外延层接触。

公开(公告)号：US6063682A

公开(公告)日：2000-05-16

申请号：US49322

申请日：1998-03-27

Applicant: Akif Sultan ,  Geoffrey Choh-Fei Yeap

Inventor： Akif Sultan ,  Geoffrey Choh-Fei Yeap

IPC: H01L21/265 ,  H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/2652 ,  Y10S438/918

Abstract: A method of fabricating a transistor is provided. According to the method, a heavy ion is implanted into a silicon substrate so as to amorphize at least a portion of the silicon substrate. The amorphized silicon is substantially free of channels. A dopant is subsequently implanted into the amorphized silicon, and the amorphized silicon substantially contains the implanted dopant. Thereafter, a silicon implanting step is performed to create an excess of vacancies to interstitials within a predetermined range. Enhanced diffusion of the dopant within the predetermined range is mitigated because of the excess of vacancies to interstitials within this predetermined range.

Abstract translation: 提供一种制造晶体管的方法。 根据该方法，将重离子注入到硅衬底中，以使至少一部分硅衬底非晶化。 非晶化硅基本上不含通道。 随后将掺杂剂注入到非晶化硅中，并且非晶化硅基本上包含注入的掺杂剂。 此后，进行硅注入步骤以在预定范围内产生过多的间隙空隙。 由于在该预定范围内间隙的空位过多，掺杂剂在预定范围内的增强扩散减轻。

公开(公告)号：US20120003802A1

公开(公告)日：2012-01-05

申请号：US13230083

申请日：2011-09-12

Applicant: Jian Chen ,  James F. Buller ,  Akif Sultan

Inventor： Jian Chen ,  James F. Buller ,  Akif Sultan

IPC: H01L21/336

CPC classification number: H01L29/78618 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7848

Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Abstract translation: 本发明涉及具有不对称硅锗源区的晶体管及其制造方法。 在一个说明性实施例中，晶体管包括形成在由硅构成的半导体衬底之上的栅电极，掺杂源区包括在半导体衬底中形成的锗掺杂的外延生长硅的区域和形成在半导体衬底中的掺杂漏极区 基质。

公开(公告)号：US08035098B1

公开(公告)日：2011-10-11

申请号：US11278618

申请日：2006-04-04

Applicant: Jian Chen ,  James F. Buller ,  Akif Sultan

Inventor： Jian Chen ,  James F. Buller ,  Akif Sultan

IPC: H01L29/06 ,  H01L21/336

CPC classification number: H01L29/78618 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7848

Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Abstract translation: 本发明涉及具有不对称硅锗源区的晶体管及其制造方法。 在一个说明性实施例中，晶体管包括形成在由硅构成的半导体衬底之上的栅电极，掺杂源区包括在半导体衬底中形成的锗掺杂的外延生长硅的区域和形成在半导体衬底中的掺杂漏极区 基质。

公开(公告)号：US07793240B2

公开(公告)日：2010-09-07

申请号：US11537390

申请日：2006-09-29

Applicant: Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

Inventor： Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.

Abstract translation: 一种方法包括接收与集成电路装置相关联的设计数据。 集成电路装置包括具有限定在其中的角部的第一元件和与第一元件重叠的第二元件。 基于第二元件和拐角之间的距离来调整为设计数据中的第一元件指定的尺寸。 基于经调整的尺寸模拟集成电路器件。

公开(公告)号：US07633103B2

公开(公告)日：2009-12-15

申请号：US11846318

申请日：2007-08-28

Applicant: Akif Sultan ,  James F. Buller ,  Kaveri Mathur

Inventor： Akif Sultan ,  James F. Buller ,  Kaveri Mathur

IPC: H01L29/76

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/7843

Abstract: A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region. The compressive layer also overlies the gate electrode finger portions, and the tensile layer is disposed adjacent the transverse edge of the active region.

Abstract translation: 提供了一种半导体器件，其包括：基板，其包括非活性区域和有源区域;栅极电极结构，其具有覆盖有源区域的部分;覆盖有源区域的压缩层;以及覆盖非活性区域并位于有源区域外部的拉伸层 地区。 有源区域具有限定有源区域的宽度的横向边缘和限定有源区域的长度的横向边缘。 栅电极结构包括：与有源区间隔开的公共部分; 与公共部分成一体的多个栅极电极指部，以及与公共部分和栅电极指部分成一体的多个圆角部分。 每个栅电极指部分的一部分覆盖有源区。 圆角部分设置在公共部分和栅极电极指部分之间，并且不覆盖有源区域。 压电层也覆盖在栅极电极指部分上，并且拉伸层邻近有源区的横向边缘设置。

公开(公告)号：US20080085570A1

公开(公告)日：2008-04-10

申请号：US11538872

申请日：2006-10-05

Applicant: Akif Sultan ,  James F. Buller ,  David Donggang Wu

Inventor： Akif Sultan ,  James F. Buller ,  David Donggang Wu

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L22/14

Abstract: A test structure includes first and second pluralities of transistors. The first plurality of transistors includes gate electrodes of a first length. The second plurality of transistors includes gate electrodes of a second length different than the first length. A channel area of the transistors in the first plurality is substantially equal to a channel area of the transistors in the second plurality. A method for using the test structure includes measuring a performance metric of the first and second pluralities of transistors. Variation in the performance metric associated with the first plurality of transistors is compared to variation in the performance metric associated with the second plurality of transistors to identify a random length variation component associated with the first plurality of transistors.

Abstract translation: 测试结构包括第一和第二多个晶体管。 第一多个晶体管包括第一长度的栅电极。 第二多个晶体管包括与第一长度不同的第二长度的栅电极。 第一多个晶体管的沟道面积基本上等于第二多个晶体管的沟道面积。 使用测试结构的方法包括测量第一和第二多个晶体管的性能度量。 将与第一多个晶体管相关联的性能度量的变化与与第二多个晶体管相关联的性能度量的变化进行比较，以识别与第一多个晶体管相关联的随机长度变化分量。