公开(公告)号：US08729669B2

公开(公告)日：2014-05-20

申请号：US13519252

申请日：2010-12-02

申请人： Le Wang ,  Linchun Gui ,  Kongwei Zhu ,  Zhiyong Zhao

发明人： Le Wang ,  Linchun Gui ,  Kongwei Zhu ,  Zhiyong Zhao

IPC分类号： H01L29/02

CPC分类号： H01L29/66272

摘要： A method for manufacturing a bipolar transistor includes forming a first epitaxial layer on a semiconductor substrate, forming a second epitaxial layer on the first epitaxial layer, forming an oxide layer on the second epitaxial layer, etching the oxide layer to form an opening in which the second epitaxial layer is exposed, and forming a third epitaxial layer in the opening. The first and third epitaxial layers have a first-type conductivity, and the second epitaxial layer has a second-type conductivity.

摘要翻译： 一种用于制造双极晶体管的方法，包括在半导体衬底上形成第一外延层，在第一外延层上形成第二外延层，在第二外延层上形成氧化层，蚀刻氧化物层以形成开口， 暴露第二外延层，并在开口中形成第三外延层。 第一和第三外延层具有第一类型的导电性，第二外延层具有第二类型的导电性。

公开(公告)号：US20120256252A1

公开(公告)日：2012-10-11

申请号：US13384002

申请日：2010-10-26

申请人： Linchun Gui ,  Le Wang ,  Zhiyong Zhao ,  Lili He

发明人： Linchun Gui ,  Le Wang ,  Zhiyong Zhao ,  Lili He

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/66712 ,  H01L21/823418 ,  H01L21/823487 ,  H01L21/8249 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7809 ,  H01L29/7835

摘要： A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region, where the P+ region is in contact with the source.

摘要翻译： 制造兼容的垂直双扩散金属氧化物半导体（VDMOS）晶体管和横向双扩散金属氧化物半导体（LDMOS）晶体管的方法包括：提供具有LDMOS晶体管区域和VDMOS晶体管区域的衬底; 在所述衬底中形成N掩埋区域; 在N掩埋层区域上形成外延层; 在LDMOS晶体管区域和VDMOS晶体管区域中形成隔离区域; 在LDMOS晶体管区域中形成漂移区; 在LDMOS晶体管区域和VDMOS晶体管区域中形成栅极; 在LDMOS晶体管区域和VDMOS晶体管区域中形成PBODY区域; 在LDMOS晶体管区域中形成N型GRADE区域; 在所述VDMOS晶体管区域中形成NSINK区域，其中所述NSINK区域与所述N埋层区域接触; 在LDMOS晶体管区域和VDMOS晶体管区域中形成源极和漏极; 以及在LDMOS晶体管区域中形成P +区域，其中P +区域与源极接触。

公开(公告)号：US07063991B1

公开(公告)日：2006-06-20

申请号：US10900832

申请日：2004-07-28

申请人： Zhiyong Zhao ,  Christian Krueger

发明人： Zhiyong Zhao ,  Christian Krueger

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G01R31/2831 ,  H01L21/26513

摘要： Disclosed herein are various methods of determining characteristics of doped regions on device wafers, and a system for accomplishing same. In one illustrative embodiment, the method includes providing a device substrate comprising a plurality of masked areas, a plurality of unmasked areas, and at least one doped region formed in the substrate, determining a ratio between the unmasked areas and the masked areas for the device substrate, illuminating an area of the device substrate comprising the masked areas, the unmasked areas, and at least one doped region, and measuring an induced surface photovoltage of the device substrate while accounting for the ratio of the unmasked areas and the masked areas of the device substrate. In another illustrative embodiment, the method includes providing an SOI substrate comprised of an active layer, the active layer having a thickness, illuminating an area of the substrate using a light source having a wavelength that is sufficiently long such that an excited region created in the active layer due to the illumination does not extend beyond the thickness of the active layer, and measuring an induced surface photovoltage resulting from the illumination.

公开(公告)号：US06852990B1

公开(公告)日：2005-02-08

申请号：US09896381

申请日：2001-06-29

申请人： Zhiyong Zhao ,  David Hendrix

发明人： Zhiyong Zhao ,  David Hendrix

IPC分类号： H01J37/02 ,  H01J61/00

CPC分类号： H01J37/026 ,  H01J2237/0041

摘要： A method for electrostatic discharge depolarization is implemented. The buildup of charge on tool structures in fabrication tools for semiconductor processing may be expected to be of concern whenever high voltage is employed near the structure in a tool. The process herein includes selectively exposing the structure to a plasma for a selected time interval. The duration of the exposure time interval is sufficient to reduce the polarization of the structure whereby the forces due to the polarization do not interfere with the transport or movement of a wafer being processed.

摘要翻译： 实现了静电放电去极化的方法。 只要在工具中的结构附近采用高电压，可以预期在半导体处理用制造工具中的工具结构上的电荷的积累。 本文的方法包括在所选择的时间间隔内将结构选择性地暴露于等离子体。 曝光时间间隔的持续时间足以减少结构的极化，由此由偏振引起的力不会干扰被处理的晶片的传输或移动。

公开(公告)号：US07504838B1

公开(公告)日：2009-03-17

申请号：US11381239

申请日：2006-05-02

申请人： Zhiyong Zhao ,  Christian Krueger

发明人： Zhiyong Zhao ,  Christian Krueger

IPC分类号： G01R31/02

CPC分类号： G01R31/2831 ,  H01L21/26513

摘要： Disclosed herein are various methods of determining characteristics of doped regions on device wafers, and a system for accomplishing same. In one illustrative embodiment, the method includes providing a device substrate comprising a plurality of masked areas, a plurality of unmasked areas, and at least one doped region formed in the substrate, determining a ratio between the unmasked areas and the masked areas for the device substrate, illuminating an area of the device substrate comprising the masked areas, the unmasked areas, and at least one doped region, and measuring an induced surface photovoltage of the device substrate while accounting for the ratio of the unmasked areas and the masked areas of the device substrate. In another illustrative embodiment, the method includes providing an SOI substrate comprised of an active layer, the active layer having a thickness, illuminating an area of the substrate using a light source having a wavelength that is sufficiently long such that an excited region created in the active layer due to the illumination does not extend beyond the thickness of the active layer, and measuring an induced surface photovoltage resulting from the illumination.

摘要翻译： 本文公开了确定器件晶片上的掺杂区域的特性的各种方法以及用于实现其的系统。 在一个说明性实施例中，该方法包括提供包括多个掩蔽区域，多个未掩模区域和形成在该衬底中的至少一个掺杂区域的器件衬底，确定该未屏蔽区域与该器件的掩蔽区域之间的比率 衬底，照射包括掩蔽区域，未掩蔽区域和至少一个掺杂区域的器件衬底的区域，以及测量器件衬底的感应表面光电压，同时考虑未掩蔽区域和掩蔽区域的掩蔽面积的比率 器件衬底。 在另一说明性实施例中，该方法包括提供由有源层构成的SOI衬底，有源层具有厚度，使用具有足够长的波长的光源照射衬底的区域，使得在 由于照明而导致的有源层不会超出有源层的厚度，并且测量由照明产生的感应表面光电压。

公开(公告)号：US06677168B1

公开(公告)日：2004-01-13

申请号：US10135703

申请日：2002-04-30

申请人： Zhiyong Zhao ,  Clive Jones

发明人： Zhiyong Zhao ,  Clive Jones

IPC分类号： G01R3126

CPC分类号： H01L21/265 ,  H01J2237/31703

摘要： Various methods of determining ion implant dosage are disclosed. In one aspect, a method of processing a semiconductor workpiece that has a device region and an inactive region is provided. A first mask is formed on a first portion of the inactive region. A first implant of ions is performed on the device region and the first mask. A secondary ion mass spectrometry analysis of the first portion of the first mask is performed to determine a composition thereof relative to a standard composition. A dose for the first implant is determined based upon the secondary ion mass spectrometry analysis of the first portion of the first mask. The first implant dose is compared with a prescribed dose for the first implant to determine if a second implant is necessary to achieve the prescribed dose, and if so, an appropriate make-up dose for the second implant.

摘要翻译： 公开了确定离子注入剂量的各种方法。 一方面，提供了具有器件区域和非工作区域的半导体工件的处理方法。 第一掩模形成在非活性区域的第一部分上。 在器件区域和第一掩模上执行第一离子注入。 进行第一掩模的第一部分的二次离子质谱分析以确定其相对于标准组合物的组成。 基于第一掩模的第一部分的二次离子质谱分析确定第一种植入物的剂量。 将第一植入剂量与用于第一植入物的规定剂量进行比较，以确定是否需要第二植入物来实现规定的剂量，如果是的话，则确定第二植入物的适当的补充剂量。

公开(公告)号：US06630677B1

公开(公告)日：2003-10-07

申请号：US09943570

申请日：2001-08-29

申请人： Zhiyong Zhao ,  David Hendrix

发明人： Zhiyong Zhao ,  David Hendrix

IPC分类号： H01J3712

CPC分类号： H01J37/12 ,  H01J37/3171

摘要： An electrostatic lens with glassy graphite electrodes for use in an ion implanter is disclosed. The graphite electrodes have been manufactured to be substantially smooth (glassy) such that irregularities on the surface grain of the graphite, for example peaks or apexes, are no longer present. In an embodiment, employing polished graphite electrostatic lens electrodes does not require the time-consuming conditioning operations under vacuum that are typically needed with conventional graphite electrodes, and thus offers the advantage of increased uptime for an ion implantation system. In addition, because surface irregularities are not present to serve as discharge points for electrostatic buildup, the use of glassy graphite electrodes as disclosed offers the advantage of electrostatic discharge reduction. Reduction of electrostatic discharge results in decreased particulate contamination from discharge events, as well as lessening of the probability of irreparable physical damage to implantation target material.

摘要翻译： 公开了一种用于离子注入机的具有玻璃状石墨电极的静电透镜。 石墨电极已被制造成基本上光滑（玻璃状），使得不再存在石墨表面晶粒上的凹凸，例如峰或顶点。 在一个实施例中，使用抛光的石墨静电透镜电极不需要在常规石墨电极通常需要的真空下的耗时的调节操作，因此提供了离子注入系统的正常运行时间增加的优点。 此外，由于不存在表面不规则性以用作静电积聚的放电点，因此所公开的玻璃状石墨电极的使用提供了静电放电还原的优点。 静电放电的减少导致放电事件引起的颗粒污染减少，以及降低对植入靶材料的不可挽回的物理损伤的可能性。