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    ERROR DETECTION ON PROGRAMMABLE LOGIC RESOURCES
    11.
    发明申请
    ERROR DETECTION ON PROGRAMMABLE LOGIC RESOURCES 有权
    对可编程逻辑资源的错误检测

    公开(公告)号：US20080052569A1

    公开(公告)日：2008-02-28

    申请号：US11930739

    申请日：2007-10-31

    Applicant: Ninh Ngo ,  Andy Lee ,  Kerry Veenstra

    Inventor： Ninh Ngo ,  Andy Lee ,  Kerry Veenstra

    IPC: G06F11/00

    CPC classification number: H03K19/17764 ,  G06F11/1004

    Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

    Abstract translation: 在可编程逻辑资源上提供错误检测电路。 可编程逻辑资源配置数据被加载到可以执行校验和计算的循环冗余校验（CRC）模块中。 在一个实施例中，校验和可以与预期值进行比较，期望值是在被编程到数据被编程到可编程逻辑资源之前或数据被编程到数据之前的预计算校验和。 在另一个实施例中，期望值可以包括在校验和计算中。 可以根据校验和和期望值之间的关系或校验和的值来生成指示是否检测到错误的输出。 该输出可以被发送到用户逻辑可访问的输出引脚。

    METHOD, SYSTEM, AND PROGRAM FOR CUSTOMER SERVICE AND SUPPORT MANAGEMENT
    12.
    发明申请
    METHOD, SYSTEM, AND PROGRAM FOR CUSTOMER SERVICE AND SUPPORT MANAGEMENT 失效
    客户服务和支持管理的方法，系统和程序

    公开(公告)号：US20080052320A1

    公开(公告)日：2008-02-28

    申请号：US11933050

    申请日：2007-10-31

    Applicant: Andy Lee ,  Hsyh-Min Hsu ,  Paul Hao ,  Shyh-Tyng Sun ,  Tracy Tseng

    Inventor： Andy Lee ,  Hsyh-Min Hsu ,  Paul Hao ,  Shyh-Tyng Sun ,  Tracy Tseng

    IPC: G06F7/00

    CPC classification number: G06F17/30286 ,  G06Q30/00 ,  Y10S707/948 ,  Y10S707/949

    Abstract: In accordance with the present invention, a method, system, and program for managing the customer and product information of a client by maintaining a common database is disclosed. The present invention connects the client, call center, repair facility and warehouse to efficiently coordinate the customer and product management process. By allowing access to a common database, a user can view and update changes in the customer and product management process in real time increasing the communication and efficiency of delivering service to a customer.

    Abstract translation: 根据本发明，公开了一种用于通过维护公共数据库来管理客户的客户和产品信息的方法，系统和程序。 本发明连接客户端，呼叫中心，维修设施和仓库，有效协调客户和产品管理流程。 通过允许访问公共数据库，用户可以实时查看和更新​​客户和产品管理过程中的更改，从而增加向客户提供服务的通信和效率。

    Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method
    13.
    发明授权
    Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method 有权
    可编程逻辑器件具有可修复电路阵列内的不可修复电路区域和相关配置硬件和方法

    公开(公告)号：US07215140B1

    公开(公告)日：2007-05-08

    申请号：US10452673

    申请日：2003-05-30

    Applicant: Rahul Saini ,  Andy Lee ,  Ninh Ngo

    Inventor： Rahul Saini ,  Andy Lee ,  Ninh Ngo

    IPC: H03K19/177

    CPC classification number: H03K19/17748 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17764

    Abstract: An embodiment of the present invention provides a programmable logic device (“PLD”) including one or more dedicated blocks of circuitry within one or more repairable logic array regions. Aspects of the present invention provide circuitry and methods for controlling shifting of programming data in normal and redundant modes for both dedicated block regions and fully repairable logic array regions during both regular and test programming sequences of a PLD. Other aspects provide circuitry and methods for interface routing between dedicated blocks and repairable logic array regions in both normal and redundant modes. Various other aspects are also disclosed.

    Abstract translation: 本发明的一个实施例提供一种可编程逻辑器件（“PLD”），其包括一个或多个可修复逻辑阵列区域内的一个或多个专用电路块。 本发明的方面提供用于在PLD的规则和测试编程序列期间控制专用块区域和完全可修复的逻辑阵列区域的正常和冗余模式中的编程数据的移位的电路和方法。 其他方面提供用于在正常模式和冗余模式中的专用块和可修复逻辑阵列区之间的接口路由的电路和方法。 还公开了各种其它方面。

    Location identification using broadcast wireless signal signatures
    14.
    发明申请
    Location identification using broadcast wireless signal signatures 有权
    使用广播无线信号签名的位置识别

    公开(公告)号：US20070050824A1

    公开(公告)日：2007-03-01

    申请号：US11284800

    申请日：2005-11-22

    Applicant: Andy Lee ,  James Spilker ,  Matthew Rabinowitz ,  Jimmy Omura

    Inventor： Andy Lee ,  James Spilker ,  Matthew Rabinowitz ,  Jimmy Omura

    IPC: H04N7/18 ,  H04N7/16

    CPC classification number: G01S5/0252 ,  H04H60/51 ,  H04W64/00

    Abstract: An apparatus having a corresponding computer program comprises a receiver to receive one or more wireless signals; and a measurement circuit to obtain measurements of one or more characteristics of each of the wireless signals; wherein one or more of a plurality of possible locations of the apparatus are selected based on the measurements and a plurality of associations each associating one of the possible locations with expected values for the measurements for the one of the possible locations.

    Abstract translation: 具有对应的计算机程序的装置包括：接收器，用于接收一个或多个无线信号; 以及测量电路，用于获得每个所述无线信号的一个或多个特性的测量值; 其中基于所述测量和多个关联来选择所述装置的多个可能位置中的一个或多个，每个关联将所述可能位置中的一个与所述可能位置之一的所述测量值的预期值相关联。

    Fracturable lookup table and logic element
    15.
    发明申请
    Fracturable lookup table and logic element 有权
    可破坏的查找表和逻辑元素

    公开(公告)号：US20060017460A1

    公开(公告)日：2006-01-26

    申请号：US11189549

    申请日：2005-07-25

    Applicant: David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

    Inventor： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

    IPC: H03K19/177

    CPC classification number: H03K19/17728 ,  H03K19/1737

    Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

    Abstract translation: 逻辑元件包括存储器元件，多路复用器和控制器。 多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输出的输出端和第一级多路复用器，其输入端连接到第二级 多路复用器和至少一个输出。 控制器连接到多路复用器。 在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出， 第一级多路复用器。

    Method and apparatus to measure internal node timing
    16.
    发明授权
    Method and apparatus to measure internal node timing 失效
    测量内部节点定时的方法和装置

    公开(公告)号：US5754063A

    公开(公告)日：1998-05-19

    申请号：US670303

    申请日：1996-06-27

    Applicant: Andy Lee

    Inventor： Andy Lee

    IPC: G01R29/027 ,  H03K5/26 ,  H03K5/19

    CPC classification number: G01R29/0273 ,  H03K5/26

    Abstract: Internal node timing on an integrated circuit which is supplied with a clock signal from a system clock, the cycle time of which can be varied is measured by connecting a sequential element such as a latch to the node to measured and clocking it with a delayed measurement clock while increasing the clock cycle time. The output of the sequential element is an output pin of said integrated circuit. The measurement clock has the same cycle time as the system clock but has a latching edge delayed, the delay being at least 1.5 times the nominal system clock cycle time when it is desired to make measurement over both the high phase and low phase. The output pin is observed and the clock cycle time at which the sequential element fails to latch the current value determined. In a further embodiment, two sequential elements are used to make two measurements of this type and the difference between the two measurements is used to compute the time delay between the two nodes being measured. One node may be a clock node. By using two such measurements the delay of the measurement clock need not be known. Because frequency is increased instead of decreased in this method and apparatus, it can be used to measure the timing of both static and dynamic circuits without affecting the normal operation of the designed circuit.

    Abstract translation: 通过将诸如锁存器的顺序元件连接到节点来测量并提供来自系统时钟的来自系统时钟的时钟信号的周期时间的内部节点定时，以便通过延迟测量来测量和计时 时钟同时增加时钟周期时间。 顺序元件的输出是所述集成电路的输出引脚。 测量时钟具有与系统时钟相同的周期时间，但是具有延迟的锁存边沿，当期望在高相位和低相位上进行测量时，延迟至少为标称系统时钟周期时间的1.5倍。 观察输出引脚以及顺序元件无法锁定当前值确定的时钟周期时间。 在另一实施例中，使用两个顺序元件进行这种类型的两个测量，并且使用两个测量之间的差来计算被测量的两个节点之间的时间延迟。 一个节点可以是时钟节点。 通过使用两个这样的测量，测量时钟的延迟不需要是已知的。 由于在该方法和装置中频率增加而不是减小，所以可以用来测量静态和动态电路的时序，而不影响设计电路的正常工作。

    Wide-lane pseudorange measurements using FM signals
    20.
    发明授权
    Wide-lane pseudorange measurements using FM signals 有权
    使用FM信号的宽行距伪距测量

    公开(公告)号：US07498873B2

    公开(公告)日：2009-03-03

    申请号：US11554765

    申请日：2006-10-31

    Applicant: Guttorm Opshaug ,  David Burgess ,  George Flammer ,  Scott Furman ,  Andy Lee ,  Matthew Rabinowitz ,  Harvind Samra

    Inventor： Guttorm Opshaug ,  David Burgess ,  George Flammer ,  Scott Furman ,  Andy Lee ,  Matthew Rabinowitz ,  Harvind Samra

    IPC: G01S1/00 ,  H03D3/00 ,  H04B1/16

    CPC classification number: G01S11/02 ,  G01S5/0263 ,  G01S5/12

    Abstract: Apparatus having corresponding methods and computer-readable media comprises a receiver to receive a wireless stereo frequency-modulation (FM) signal comprising a plurality of spectral signal components including a first tone and one or more frequency bands; one or more tone generators each to generate a respective second tone based on a respective one of the frequency bands; a plurality of phase circuits each to measure a phase of a respective one of the first and second tones; and a difference element to determine a phase difference between two of the phases.

    Abstract translation: 具有相应方法和计算机可读介质的装置包括：接收器，用于接收包括包括第一音调和一个或多个频带的多个频谱信号分量的无线立体声调频（FM）信号; 一个或多个音调发生器，每个音调发生器基于相应的一个频带产生相应的第二音调; 多个相位电路，各自测量第一和第二音调中的相应一个的相位; 以及差分元件，以确定两相之间的相位差。

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