公开(公告)号：US20050144386A1

公开(公告)日：2005-06-30

申请号：US10747470

申请日：2003-12-29

Applicant: Ali-Reza Adl-Tabatabai ,  Anwar Ghuloum ,  Guei-Yuan Lueh ,  Victor Ying

Inventor： Ali-Reza Adl-Tabatabai ,  Anwar Ghuloum ,  Guei-Yuan Lueh ,  Victor Ying

IPC: G06F12/08 ,  H03M7/30 ,  G06F12/00

CPC classification number: G06F12/0802 ,  G06F12/0862 ,  G06F2212/401 ,  H03M7/30

Abstract: According to one embodiment a computer system is disclosed. The computer system includes a central processing unit (CPU), a cache memory coupled to the CPU and a cache controller, coupled to the cache memory. The cache memory includes a plurality of compressible cache lines to store additional data. The cache controller reorders a cache line after each access to the cache line prior to the compression of the cache line into a compressed cache line.

Abstract translation: 根据一个实施例，公开了一种计算机系统。 计算机系统包括中央处理单元（CPU），耦合到CPU的高速缓冲存储器和耦合到高速缓冲存储器的高速缓存控制器。 高速缓冲存储器包括多个可压缩的高速缓存线以存储附加数据。 在将高速缓存行压缩到压缩高速缓存行之前，高速缓存控制器在对高速缓存行进行每次访问之后重新排序高速缓存行。

公开(公告)号：US20050071566A1

公开(公告)日：2005-03-31

申请号：US10676478

申请日：2003-09-30

Applicant: Ali-Reza Adl-Tabatabai ,  Anwar Ghuloum ,  Eric Sprangle

Inventor： Ali-Reza Adl-Tabatabai ,  Anwar Ghuloum ,  Eric Sprangle

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0886 ,  G06F2212/401

Abstract: According to one embodiment a computer system is disclosed. The computer system includes a central processing unit (CPU) and a cache memory coupled to the CPU. The cache memory includes a main cache having plurality of compressible cache lines to store additional data, and a plurality of storage pools to hold a segment of the additional data for one or more of the plurality of cache lines that are to be compressed.

Abstract translation: 根据一个实施例，公开了一种计算机系统。 计算机系统包括中央处理单元（CPU）和耦合到CPU的高速缓冲存储器。 高速缓冲存储器包括具有多个可压缩高速缓存行以存储附加数据的主高速缓存，以及多个存储池，用于保存要被压缩的多个高速缓存行中的一个或多个的附加数据的段。

公开(公告)号：US08627301B2

公开(公告)日：2014-01-07

申请号：US11750441

申请日：2007-05-18

Applicant: Matthew Hammer ,  Mohan Rajagopalan ,  Anwar Ghuloum

Inventor： Matthew Hammer ,  Mohan Rajagopalan ,  Anwar Ghuloum

IPC: G06F9/44 ,  G06F9/45

CPC classification number: G06F9/5066

Abstract: A method for concurrent management of adaptive programs is disclosed wherein changes in a set of modifiable references are initially identified. A list of uses of the changed references is next computed using records made in structures of the references. The list is next inserted into an elimination queue. Comparison is next made of each of the uses to the other uses to determine independence or dependence thereon. Determined dependent uses are eliminated and the preceding steps are repeated for all determined independent uses until all dependencies have been eliminated.

Abstract translation: 公开了一种用于并行管理自适应程序的方法，其中初始地识别一组可修改参考文献中的改变。 接下来使用在引用的结构中作出的记录来计算更改的引用的使用列表。 列表接下来插入消除队列。 下一步将对其他用途的各种用途进行比较，以确定其独立性或依赖性。 消除确定的依赖用途，并且对于所有确定的独立使用重复前述步骤，直到所有依赖关系被消除。

公开(公告)号：US20090235273A1

公开(公告)日：2009-09-17

申请号：US12049914

申请日：2008-03-17

Applicant: Leaf Petersen ,  Anwar Ghuloum ,  Mohan Rajagopalan

Inventor： Leaf Petersen ,  Anwar Ghuloum ,  Mohan Rajagopalan

IPC: G06F9/46

CPC classification number: G06F9/524

Abstract: A method for evaluating objects in a data structure is provided. The method comprises assigning one or more objects to one or more nodes in a data structure having at least a root node, wherein the objects are assigned to the nodes in accordance with a first order to maintain pre-existing dependencies between said objects and to allow the objects to be evaluated in a serial manner to avoid deadlock when concurrently executing threads to evaluate the objects; and selecting a first object for evaluation, in response to determining that the current object is unevaluated.

Abstract translation: 提供了一种用于评估数据结构中的对象的方法。 该方法包括将一个或多个对象分配给具有至少根节点的数据结构中的一个或多个节点，其中根据第一顺序将对象分配给节点，以维持所述对象之间的预先存在的依赖关系并允许 要以串行方式评估的对象，以在同时执行线程来评估对象时避免死锁; 以及响应于确定当前对象未被评估，选择用于评估的第一对象。

公开(公告)号：US20060047916A1

公开(公告)日：2006-03-02

申请号：US10930882

申请日：2004-08-31

Applicant: Zhiwei Ying ,  Guei-Yuan Lueh ,  Jinzhan Peng ,  Anwar Ghuloum ,  Ali-Reza Adl-Tabatabai

Inventor： Zhiwei Ying ,  Guei-Yuan Lueh ,  Jinzhan Peng ,  Anwar Ghuloum ,  Ali-Reza Adl-Tabatabai

IPC: G06F12/00

CPC classification number: G06F12/0802 ,  G06F12/123 ,  G06F2212/401

Abstract: In one embodiment, the present invention includes a cache memory having a plurality of cache lines to store data, in which at least some of the cache lines are adapted to store data in a compressed state. The cache memory also may include a first tag corresponding to each of the cache lines to indicate whether data in the corresponding cache line is compressible.

Abstract translation: 在一个实施例中，本发明包括具有多条高速缓存行以存储数据的高速缓存存储器，其中至少一些高速缓存行适于以压缩状态存储数据。 高速缓冲存储器还可以包括对应于每个高速缓存行的第一标签，以指示对应的高速缓存行中的数据是否是可压缩的。

公开(公告)号：US20050149521A1

公开(公告)日：2005-07-07

申请号：US10746421

申请日：2003-12-24

Applicant: Hong Wang ,  John Shen ,  Ali-Reza Adl-Tabatabai ,  Anwar Ghuloum

Inventor： Hong Wang ,  John Shen ,  Ali-Reza Adl-Tabatabai ,  Anwar Ghuloum

IPC: G06F9/45 ,  G06F17/30

CPC classification number: G06F9/30181 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  Y10S707/99931

Abstract: In one embodiment, the invention provides a method comprising determining metadata encoded in instructions of a stored program; and executing the stored program based on the metadata.

Abstract translation: 在一个实施例中，本发明提供了一种方法，包括确定在存储的节目的指令中编码的元数据; 以及基于所述元数据执行所存储的程序。

公开(公告)号：US20050144388A1

公开(公告)日：2005-06-30

申请号：US10750715

申请日：2003-12-31

Applicant: Chris Newburn ,  Ram Huggahalli ,  Herbert Hum ,  Ali-Reza Adl-Tabatabai ,  Anwar Ghuloum

Inventor： Chris Newburn ,  Ram Huggahalli ,  Herbert Hum ,  Ali-Reza Adl-Tabatabai ,  Anwar Ghuloum

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0802 ,  G06F12/0886 ,  G06F2212/401

Abstract: A memory controller is described that comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information. A processor and a memory controller integrated on a same semiconductor die is also described. The memory controller comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information.

Abstract translation: 描述了包括压缩映射高速缓存的存储器控​​制器。 压缩映射缓存用于存储标识缓存行的信息值的信息，该信息已被另一个高速缓存行的信息压缩。 还描述了集成在同一半导体管芯上的处理器和存储器控制器。 存储器控制器包括压缩映射高速缓存。 压缩映射缓存用于存储标识缓存行的信息值的信息，该信息已被另一个高速缓存行的信息压缩。

公开(公告)号：US08312225B2

公开(公告)日：2012-11-13

申请号：US13156777

申请日：2011-06-09

Applicant: Joshua B. Fryman ,  Mohan Rajagopalan ,  Anwar Ghuloum

Inventor： Joshua B. Fryman ,  Mohan Rajagopalan ,  Anwar Ghuloum

IPC: G06F12/00

CPC classification number: G06F12/0817 ,  G06F12/0822

Abstract: In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，具有每个与高速缓存存储器相关联的核心的多核处理器可以操作，使得当第一核心要访问存在于与第二核心相关联的高速缓存行中的第二核心拥有的数据时，响应于请求 从第一核心，与高速缓存行相关联的高速缓存一致性状态信息不被更新。 与处理器相关联的相干引擎可以接收数据访问请求，并确定数据是由第一核心拥有的存储器页面，并将数据访问请求转换为非高速缓存一致性请求。 描述和要求保护其他实施例。

公开(公告)号：US20110238926A1

公开(公告)日：2011-09-29

申请号：US13156777

申请日：2011-06-09

Applicant: Joshua B. Fryman ,  Mohan Rajagopalan ,  Anwar Ghuloum

Inventor： Joshua B. Fryman ,  Mohan Rajagopalan ,  Anwar Ghuloum

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F12/0822

Abstract: In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，具有每个与高速缓存存储器相关联的核心的多核处理器可以操作，使得当第一核心要访问存在于与第二核心相关联的高速缓存行中的第二核心拥有的数据时，响应于请求 从第一核心，与高速缓存行相关联的高速缓存一致性状态信息不被更新。 与处理器相关联的相干引擎可以接收数据访问请求，并确定数据是由第一核心拥有的存储器页面，并将数据访问请求转换为非高速缓存一致性请求。 描述和要求保护其他实施例。

公开(公告)号：US07984244B2

公开(公告)日：2011-07-19

申请号：US12005785

申请日：2007-12-28

Applicant: Joshua B. Fryman ,  Mohan Rajagopalan ,  Anwar Ghuloum

Inventor： Joshua B. Fryman ,  Mohan Rajagopalan ,  Anwar Ghuloum

IPC: G06F12/00

CPC classification number: G06F12/0817 ,  G06F12/0822

Abstract: In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，具有每个与高速缓存存储器相关联的核心的多核处理器可以操作，使得当第一核心要访问存在于与第二核心相关联的高速缓存行中的第二核心拥有的数据时，响应于请求 从第一核心，与高速缓存行相关联的高速缓存一致性状态信息不被更新。 与处理器相关联的相干引擎可以接收数据访问请求，并确定数据是由第一核心拥有的存储器页面，并将数据访问请求转换为非高速缓存一致性请求。 描述和要求保护其他实施例。