公开(公告)号：US11841726B2

公开(公告)日：2023-12-12

申请号：US17181950

申请日：2021-02-22

Applicant: Apple Inc.

Inventor： Seyedeh Sedigheh Hashemi ,  Vahid Majidzadeh Bafar ,  Ali Mesgarani ,  Mansour Keramat

IPC: G05F3/26 ,  G05F3/20 ,  G11C5/14 ,  G11C11/4074

CPC classification number: G05F3/26 ,  G05F3/205 ,  G11C5/147 ,  G11C11/4074

Abstract: A power detect circuit is disclosed. A power detect circuit includes a voltage multiplier that receives an external supply voltage and generates a second supply voltage that is greater than the former. A voltage regulator is coupled to receive the second supply voltage and outputs a regulated supply voltage. A bandgap circuit is coupled to receive the second supply voltage when a first switch is closed, and the regulated supply voltage when a second switch is closed. The bandgap circuit generates a reference voltage for the voltage regulator, as well as one or more output voltages. A comparator circuit is coupled to receive the one or more output voltages from the bandgap circuit, and may compare these one or more output voltages to the regulated supply voltage.

公开(公告)号：US10937730B2

公开(公告)日：2021-03-02

申请号：US16883831

申请日：2020-05-26

Applicant: Apple Inc.

Inventor： Yi Chun A. Fu ,  Mansour Keramat ,  Vijay Srinivas

IPC: H01L23/522 ,  H01G4/01 ,  H01G4/228 ,  H01L49/02 ,  H01G4/38 ,  H03M1/20 ,  H03M1/46 ,  H01G4/06 ,  H03M1/80

Abstract: Capacitor structures with pitch-matched capacitor unit cells are described. In an embodiment, the capacitor unit cells are formed by interdigitated finger electrodes. The finger electrodes may be pitch-matched in multiple metal layers within a capacitor unit cell, and the finger electrodes may be pitch-matched among an array of capacitor unit cells. Additionally, border unit cells may be pitch-matched with the capacitor unit cells.

公开(公告)号：US20200286824A1

公开(公告)日：2020-09-10

申请号：US16883831

申请日：2020-05-26

Applicant: Apple Inc.

Inventor： Yi Chun A. Fu ,  Mansour Keramat ,  Vijay Srinivas

IPC: H01L23/522 ,  H01G4/01 ,  H01G4/228 ,  H01L49/02 ,  H01G4/38 ,  H03M1/20 ,  H03M1/46 ,  H01G4/06 ,  H03M1/80

Abstract: Capacitor structures with pitch-matched capacitor unit cells are described. In an embodiment, the capacitor unit cells are formed by interdigitated finger electrodes. The finger electrodes may be pitch-matched in multiple metal layers within a capacitor unit cell, and the finger electrodes may be pitch-matched among an array of capacitor unit cells. Additionally, border unit cells may be pitch-matched with the capacitor unit cells.

公开(公告)号：US20200043846A1

公开(公告)日：2020-02-06

申请号：US16599011

申请日：2019-10-10

Applicant: Apple Inc.

Inventor： Yi Chun A. Fu ,  Mansour Keramat ,  Vijay Srinivas

IPC: H01L23/522 ,  H01G4/01 ,  H01G4/228 ,  H01L49/02 ,  H01G4/38 ,  H03M1/20 ,  H03M1/46 ,  H01G4/06 ,  H03M1/80

Abstract: Capacitor structures with pitch-matched capacitor unit cells are described. In an embodiment, the capacitor unit cells are formed by interdigitated finger electrodes. The finger electrodes may be pitch-matched in multiple metal layers within a capacitor unit cell, and the finger electrodes may be pitch-matched among an array of capacitor unit cells. Additionally, border unit cells may be pitch-matched with the capacitor unit cells.

公开(公告)号：US09191019B2

公开(公告)日：2015-11-17

申请号：US14658333

申请日：2015-03-16

Applicant: Apple Inc.

Inventor： Mansour Keramat ,  Friedel Gerfers

IPC: H03M1/66 ,  H03M1/08 ,  H03M1/00 ,  H03M1/70 ,  H03M1/36 ,  H03M1/12

CPC classification number: H03M1/08 ,  H03M1/002 ,  H03M1/0617 ,  H03M1/121 ,  H03M1/1245 ,  H03M1/167 ,  H03M1/36 ,  H03M1/70

Abstract: In an embodiment, multiple MDAC stages are coupled in parallel to form an MDAC having the desired gain and capacitor size. Each stage may include capacitors and an OTA that are much smaller than the corresponding capacitors and OTA would be for a large single stage. Interconnect for each stage may be shorter than the single stage case, and thus the parasitic resistance and capacitance may be lower. Power consumption may be reduced, and performance of the amplifier may be increased, due to the reduced parasitic resistance and capacitance. The area occupied by the circuitry may be lower as well. Process variation within a given stage may be lower. The process variation between stages may induce noise in the output, but the parallel connection of the stages may serve to reduce the noise, in some embodiments.

Abstract translation: 在一个实施例中，多个MDAC级并联耦合以形成具有所需增益和电容器大小的MDAC。 每个阶段可以包括电容器和比对应的电容器小得多的OTA，并且OTA将用于大的单级。 每个级的互连可能比单级情况短，因此寄生电阻和电容可能较低。 由于降低的寄生电阻和电容，功耗可能会降低，放大器的性能可能会增加。 电路占用的面积也可能较低。 给定阶段内的工艺变化可能较低。 在一些实施例中，级之间的过程变化可能导致输出中的噪声，但是级的并联可以用于减少噪声。

公开(公告)号：US20150263745A1

公开(公告)日：2015-09-17

申请号：US14658333

申请日：2015-03-16

Applicant: Apple Inc.

Inventor： Mansour Keramat ,  Friedel Gerfers

IPC: H03M1/08 ,  H03M1/12 ,  H03M1/36 ,  H03M1/00 ,  H03M1/70

CPC classification number: H03M1/08 ,  H03M1/002 ,  H03M1/0617 ,  H03M1/121 ,  H03M1/1245 ,  H03M1/167 ,  H03M1/36 ,  H03M1/70

Abstract: In an embodiment, multiple MDAC stages are coupled in parallel to form an MDAC having the desired gain and capacitor size. Each stage may include capacitors and an OTA that are much smaller than the corresponding capacitors and OTA would be for a large single stage. Interconnect for each stage may be shorter than the single stage case, and thus the parasitic resistance and capacitance may be lower. Power consumption may be reduced, and performance of the amplifier may be increased, due to the reduced parasitic resistance and capacitance. The area occupied by the circuitry may be lower as well. Process variation within a given stage may be lower. The process variation between stages may induce noise in the output, but the parallel connection of the stages may serve to reduce the noise, in some embodiments.

Abstract translation: 在一个实施例中，多个MDAC级并联耦合以形成具有所需增益和电容器大小的MDAC。 每个阶段可以包括电容器和比对应的电容器小得多的OTA，并且OTA将用于大的单级。 每个级的互连可能比单级情况短，因此寄生电阻和电容可能较低。 由于降低的寄生电阻和电容，功耗可能会降低，放大器的性能可能会增加。 电路占用的面积也可能较低。 给定阶段内的工艺变化可能较低。 在一些实施例中，级之间的过程变化可能导致输出中的噪声，但是级的并联可以用于减少噪声。

公开(公告)号：US12216484B2

公开(公告)日：2025-02-04

申请号：US18340759

申请日：2023-06-23

Applicant: Apple Inc.

Inventor： Sechang Oh ,  Soheil Golara ,  Denis C. Daly ,  Seyedeh Sedigheh Hashemi ,  Mansour Keramat

IPC: G06F1/26 ,  G05F1/46 ,  G05F1/56

Abstract: A voltage reference circuit included in a computer system includes an asymmetric amplifier circuit that includes two metal-oxide semiconductor field-effect transistors with different threshold voltages. The voltage reference circuit also includes an output circuit that generates, using a control signal, a bias signal and an output current that is used by a divider circuit to generate a reference voltage and a feedback voltage. The reference voltage and bias signal are used by the amplifier circuit to generate the control signal, which is based on a difference between the transistors' threshold voltages.

公开(公告)号：US12079022B2

公开(公告)日：2024-09-03

申请号：US18493796

申请日：2023-10-24

Applicant: Apple Inc.

Inventor： Seyedeh Sedigheh Hashemi ,  Vahid Majidzadeh Bafar ,  Ali Mesgarani ,  Mansour Keramat

IPC: G05F3/26 ,  G05F3/20 ,  G11C5/14 ,  G11C11/4074

CPC classification number: G05F3/26 ,  G05F3/205 ,  G11C5/147 ,  G11C11/4074

Abstract: A power detect circuit is disclosed. A power detect circuit includes a voltage multiplier that receives an external supply voltage and generates a second supply voltage that is greater than the former. A voltage regulator is coupled to receive the second supply voltage and outputs a regulated supply voltage. A bandgap circuit is coupled to receive the second supply voltage when a first switch is closed, and the regulated supply voltage when a second switch is closed. The bandgap circuit generates a reference voltage for the voltage regulator, as well as one or more output voltages. A comparator circuit is coupled to receive the one or more output voltages from the bandgap circuit, and may compare these one or more output voltages to the regulated supply voltage.

公开(公告)号：US20220357212A1

公开(公告)日：2022-11-10

申请号：US17313844

申请日：2021-05-06

Applicant: Apple Inc.

Inventor： Ali Mesgarani ,  Farzan Farbiz ,  Ke Yun ,  Dusan Stepanovic ,  Seyedeh Sedigheh Hashemi ,  Mansour Keramat

IPC: G01K7/16 ,  H01L21/66

Abstract: A sensor system included in an integrated circuit includes multiple sensor circuits and a control circuit. Using characterization data, a model may be generated that defines a relationship between measurable parameters of the integrated circuit and an operating characteristic of the integrated circuit. The control circuit can combine, using a function included in the model, data from the multiple sensor circuits to determine a value of the operating characteristic that is more accurate than a sensor circuit configured to measure a single parameter of the integrated circuit that varies with the operating characteristic.

公开(公告)号：US11296599B1

公开(公告)日：2022-04-05

申请号：US17235718

申请日：2021-04-20

Applicant: Apple Inc.

Inventor： Soheil Golara ,  Ali Mesgarani ,  Seyedeh Sedigheh Hashemi ,  Mansour Keramat

IPC: H02M3/07 ,  G05F3/26 ,  G05F1/46

Abstract: A power supply circuit included in a computer system regulates a power supply voltage using an input power supply. During startup, the power supply circuit uses a first reference voltage that is generated using the input power supply to regulated the power supply voltage. After a period of time has elapsed, the power supply circuit switches to using a more accurate second reference voltage that is generated using the regulated power supply voltage.