中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

29 records (took 0.018 seconds)

    Hashing with Soft Memory Folding
    11.
    发明申请
    Hashing with Soft Memory Folding 有权

    公开(公告)号：US20220342806A1

    公开(公告)日：2022-10-27

    申请号：US17519284

    申请日：2021-11-04

    Applicant: Apple Inc.

    Inventor： Steven Fishwick ,  Jeffry E. Gonion ,  Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Gerard R. Williams, III

    IPC: G06F12/02 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1045

    Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

    Address Bit Dropping to Create Compacted Pipe Address for a Memory Controller
    15.
    发明申请
    Address Bit Dropping to Create Compacted Pipe Address for a Memory Controller 有权

    公开(公告)号：US20220342805A1

    公开(公告)日：2022-10-27

    申请号：US17353371

    申请日：2021-06-21

    Applicant: Apple Inc.

    Inventor： Steven Fishwick

    IPC: G06F12/02 ,  G06F12/1018 ,  G06F12/06 ,  G06F13/16

    Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

    Geometry Kick Distribution in Graphics Processor
    17.
    发明公开
    Geometry Kick Distribution in Graphics Processor 审中-公开

    公开(公告)号：US20240273667A1

    公开(公告)日：2024-08-15

    申请号：US18450964

    申请日：2023-08-16

    Applicant: Apple Inc.

    Inventor： Arjun Thottappilly ,  Steven Fishwick ,  Jason D. Carroll

    IPC: G06T1/20 ,  G06F9/50

    CPC classification number: G06T1/20 ,  G06F9/5061 ,  G06F2209/503

    Abstract: Disclosed techniques relate to parsing and assigning sets of geometry work to distributed hardware slots. In some embodiments, graphics control circuitry implements a plurality of logical slots. Control circuitry may assign a parse version of a set of geometry work to distributed hardware slots of one or more of the graphics processor sub-units that each implement multiple distributed hardware slots. Control circuitry may determine a number of segments for the set of geometry work based on execution of the parse version and assign determined segments to distributed hardware slots of respective graphics processor sub-units for execution. Stitch circuitry may stitch results of the segments processed by the assigned distributed hardware slots.

    Kickslot Manager Circuitry for Graphics Processors
    18.
    发明申请
    Kickslot Manager Circuitry for Graphics Processors 有权

    公开(公告)号：US20230048951A1

    公开(公告)日：2023-02-16

    申请号：US17399808

    申请日：2021-08-11

    Applicant: Apple Inc.

    Inventor： Steven Fishwick ,  Fergus W. MacGarry ,  Jonathan M. Redshaw ,  David A. Gotwalt ,  Ali Rabbani Rankouhi ,  Benjamin Bowman

    IPC: G06F9/50 ,  G06T1/20 ,  G06T1/60

    Abstract: Disclosed embodiments relate to controlling sets of graphics work (e.g., kicks) assigned to graphics processor circuitry. In some embodiments, tracking slot circuitry implements entries for multiple tracking slots. Slot manager circuitry may store, using an entry of the tracking slot circuitry, software-specified information for a set of graphics work, where the information includes: type of work, dependencies on other sets of graphics work, and location of data for the set of graphics work. The slot manager circuitry may prefetch, from the location and prior to allocating shader core resources for the set of graphics work, configuration register data for the set of graphics work. Control circuitry may program configuration registers for the set of graphics work using the prefetched data and initiate processing of the set of graphics work by the graphics processor circuitry according to the dependencies. Disclosed techniques may reduce kick-to-kick transition time, in some embodiments.

    Address Hashing in a Multiple Memory Controller System
    19.
    发明申请
    Address Hashing in a Multiple Memory Controller System 有权

    公开(公告)号：US20220342588A1

    公开(公告)日：2022-10-27

    申请号：US17353349

    申请日：2021-06-21

    Applicant: Apple Inc.

    Inventor： Steven Fishwick

    IPC: G06F3/06

    Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

    Cache filtering
    20.
    发明授权
    Cache filtering 有权

    公开(公告)号：US11256629B2

    公开(公告)日：2022-02-22

    申请号：US17027271

    申请日：2020-09-21

    Applicant: Apple Inc.

    Inventor： Karthik Ramani ,  Fang Liu ,  Steven Fishwick ,  Jonathan M. Redshaw

    IPC: G06F12/08 ,  G06F12/0888 ,  G06F12/0815 ,  G06F12/0877

    Abstract: Techniques are disclosed relating to filtering cache accesses. In some embodiments, a control unit is configured to, in response to a request to process a set of data, determine a size of a portion of the set of data to be handled using a cache. In some embodiments, the control unit is configured to determine filtering parameters indicative of a set of addresses corresponding to the determined size. In some embodiments, the control unit is configured to process one or more access requests for the set of data based on the determined filter parameters, including: using the cache to process one or more access requests having addresses in the set of addresses and bypassing the cache to access a backing memory directly, for access requests having addresses that are not in the set of addresses. The disclosed techniques may reduce average memory bandwidth or peak memory bandwidth.

Patent Agency Ranking