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公开(公告)号：US12052038B2
公开(公告)日：2024-07-30
申请号：US18302513
申请日：2023-04-18
Applicant: Apple Inc.
Inventor： Tyson J. Bergland , Karthik Ramani , Stephan Lachowsky , Justin A. Hensley , Davoud A. Jamshidi
IPC: H03M7/30 , H04N19/176 , H04N19/182
CPC classification number: H03M7/3059 , H04N19/176 , H04N19/182
Abstract: Techniques are disclosed relating to compression of pixel data using different quantization for different regions of a block of pixels being compressed. In some embodiments, compression circuitry is configured to determine, for multiple components included in pixels of the block of pixels being compressed, respective smallest and greatest component values in respective regions of the block of pixels. The compression circuitry may determine, based on the determined smallest and greatest component values, to use a first number of bits to represent delta values relative to a base value for a first component in a first region and a second, different number of bits to represent delta values relative to a base value for a second component in the first region. The compression circuitry may then quantize delta values for the first and second components of pixels in the first region of the block of pixels using the determined first and second numbers of bits. In some embodiments, the compression circuitry determines whether to provide cross-component bit sharing within a region.
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公开(公告)号：US11843788B2
公开(公告)日：2023-12-12
申请号：US17816136
申请日：2022-07-29
Applicant: Apple Inc.
Inventor： Tyson J. Bergland , Anthony P. DeLaurier , Karthik Ramani , Stephan Lachowsky
IPC: H04N11/02 , H04N19/182 , H03M7/30
CPC classification number: H04N19/182 , H03M7/3059
Abstract: Techniques are disclosed relating to data compression. In some embodiments, compression circuitry determines, at least partially in parallel for multiple different lossless compression techniques, amounts of data needed to represent, using a given lossless compression technique of the multiple lossless compression techniques, individual pixels in a set of pixels being compressed. The compression techniques may include neighbor, origin, and gradient techniques, for example. The compression circuitry may select one of the compression techniques based on comparison, among the compression techniques, of sums of: the determined amount of data for an individual pixel for a given lossless compression technique and compression metadata size for a given lossless compression technique. The compression circuitry may generate and store information that encodes values for the set of pixels using the selected compression technique.
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公开(公告)号：US11488350B2
公开(公告)日：2022-11-01
申请号：US17338846
申请日：2021-06-04
Applicant: Apple Inc.
Inventor： Anthony P. DeLaurier , Karl D. Mann , Tyson J. Bergland , Winnie W. Yeung
Abstract: Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, a memory system implements a storage hierarchy that includes first cache circuitry and second cache circuitry at different levels of the hierarchy. Processor circuitry generates write data to be written to the memory system. In some embodiments, first compression circuitry is configured to compress a first block of write data in response to full accumulation of the first block in the first cache circuitry and second compression circuitry is configured to compress a second block of write data in response to full accumulation of the second block in the second cache circuitry. Write circuitry may write the first and second compressed blocks of data in a single combined write to a higher level in the storage hierarchy.
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Patent Agency Ranking
公开(公告)号：US11257278B2
公开(公告)日：2022-02-22
申请号：US16953021
申请日：2020-11-19
Applicant: Apple Inc.
Inventor： Anthony P. DeLaurier , Michael J. Swift , Michal Valient , Robert S. Hartog , Tyson J. Bergland , Gokhan Avkarogullari
IPC: G06F12/1009 , G06T1/60 , G06T15/04 , G06F9/38 , G06T15/00 , G06F12/0811 , G06F9/50 , G06T11/00
Abstract: Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.
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公开(公告)号：US20250104181A1
公开(公告)日：2025-03-27
申请号：US18795437
申请日：2024-08-06
Applicant: Apple Inc.
Inventor： Karthik Ramani , Tyson J. Bergland , Leela Kishore Kothamasu , Hongzhou Zhao , Winnie W. Yeung , Mladen Wilder
IPC: G06T1/60 , G06F12/0891 , G06T15/00
Abstract: Techniques are disclosed relating to data compression in graphics processors. In some embodiments, cache circuitry is coupled to shader processor circuitry and is configured to store graphics data that includes a compressed block of data associated with a surface and metadata for the compressed block of data. Metadata coherence circuitry may cache the metadata for the compressed block of data, receive an indication of a write command for non-compressed data associated with the surface, wherein the write command identifies the metadata and has a different address than the compressed block of data, and determine, based on the metadata and the indication, to invalidate the compressed block of data in the cache circuitry. This may maintain read/write coherence in a cache that stores both compressed and uncompressed data, in some embodiments.
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公开(公告)号：US20230253979A1
公开(公告)日：2023-08-10
申请号：US18302513
申请日：2023-04-18
Applicant: Apple Inc.
Inventor： Tyson J. Bergland , Karthik Ramani , Stephan Lachowsky , Justin A. Hensley , Davoud A. Jamshidi
IPC: H03M7/30 , H04N19/182 , H04N19/176
CPC classification number: H03M7/3059 , H04N19/182 , H04N19/176
Abstract: Techniques are disclosed relating to compression of pixel data using different quantization for different regions of a block of pixels being compressed. In some embodiments, compression circuitry is configured to determine, for multiple components included in pixels of the block of pixels being compressed, respective smallest and greatest component values in respective regions of the block of pixels. The compression circuitry may determine, based on the determined smallest and greatest component values, to use a first number of bits to represent delta values relative to a base value for a first component in a first region and a second, different number of bits to represent delta values relative to a base value for a second component in the first region. The compression circuitry may then quantize delta values for the first and second components of pixels in the first region of the block of pixels using the determined first and second numbers of bits. In some embodiments, the compression circuitry determines whether to provide cross-component bit sharing within a region.
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公开(公告)号：US11664816B2
公开(公告)日：2023-05-30
申请号：US16855540
申请日：2020-04-22
Applicant: Apple Inc.
Inventor： Tyson J. Bergland , Karthik Ramani , Stephan Lachowsky , Justin A. Hensley , Davoud A. Jamshidi
IPC: H03M7/30 , H04N19/182 , H04N19/176
CPC classification number: H03M7/3059 , H04N19/176 , H04N19/182
Abstract: Techniques are disclosed relating to compression of pixel data using different quantization for different regions of a block of pixels being compressed. In some embodiments, compression circuitry is configured to determine, for multiple components included in pixels of the block of pixels being compressed, respective smallest and greatest component values in respective regions of the block of pixels. The compression circuitry may determine, based on the determined smallest and greatest component values, to use a first number of bits to represent delta values relative to a base value for a first component in a first region and a second, different number of bits to represent delta values relative to a base value for a second component in the first region. The compression circuitry may then quantize delta values for the first and second components of pixels in the first region of the block of pixels using the determined first and second numbers of bits. In some embodiments, the compression circuitry determines whether to provide cross-component bit sharing within a region.
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公开(公告)号：US11062507B2
公开(公告)日：2021-07-13
申请号：US16673883
申请日：2019-11-04
Applicant: Apple Inc.
Inventor： Anthony P. DeLaurier , Karl D. Mann , Tyson J. Bergland , Winnie W. Yeung
Abstract: Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, programmable shader circuitry is configured to execute program instructions of compute kernels that write pixel data. In some embodiments, a first cache is configured to store pixel write data from the programmable shader circuitry and first compression circuitry is configured to compress a first block of pixel write data in response to full accumulation of the first block in the first cache circuitry. In some embodiments, second cache circuitry is configured to store pixel write data from the programmable shader circuitry at a higher level in a storage hierarchy than the first cache circuitry and second compression circuitry is configured to compress a second block of pixel write data in response to full accumulation of the second block in the second cache circuitry. In some embodiments, write circuitry is configured to write the first and second compressed blocks of pixel data in a combined write to a higher level in the storage hierarchy.
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