公开(公告)号：US11418194B2

公开(公告)日：2022-08-16

申请号：US17399933

申请日：2021-08-11

Applicant: Apple Inc.

Inventor： Keith Cox ,  Victor Zyuban ,  Norman J. Rohrer

IPC: H02J1/00 ,  H03K19/0175 ,  H03K5/01 ,  G11C5/14 ,  H03K5/00 ,  H02J1/08

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

公开(公告)号：US20210376831A1

公开(公告)日：2021-12-02

申请号：US17399933

申请日：2021-08-11

Applicant: Apple Inc.

Inventor： Keith Cox ,  Victor Zyuban ,  Norman J. Rohrer

IPC: H03K19/0175 ,  H03K5/01 ,  G11C5/14

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

公开(公告)号：US20210250019A1

公开(公告)日：2021-08-12

申请号：US17245623

申请日：2021-04-30

Applicant: Apple Inc.

Inventor： Greg M. Hess ,  Vivekanandan Venugopal ,  Victor Zyuban

IPC: H03K3/037 ,  H03K3/356 ,  G11C19/18

Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.

公开(公告)号：US11005459B1

公开(公告)日：2021-05-11

申请号：US16391085

申请日：2019-04-22

Applicant: Apple Inc.

Inventor： Greg M. Hess ,  Vivekanandan Venugopal ,  Victor Zyuban

IPC: H03K3/037 ,  G11C19/18 ,  H03K3/356

Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.

公开(公告)号：US20210028785A1

公开(公告)日：2021-01-28

申请号：US17008559

申请日：2020-08-31

Applicant: Apple Inc.

Inventor： Keith Cox ,  Victor Zyuban ,  Norman J. Rohrer

IPC: H03K19/0175 ,  H03K5/01 ,  G11C5/14

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

公开(公告)号：US20180026613A1

公开(公告)日：2018-01-25

申请号：US15217122

申请日：2016-07-22

Applicant: Apple Inc.

Inventor： Victor Zyuban ,  Norman Rohrer ,  Nimish Kabe ,  Neela Lohith Penmetsa

IPC: H03K5/05 ,  H03K3/037 ,  H03K19/21

CPC classification number: H03K5/05 ,  H03K3/037 ,  H03K5/131 ,  H03K19/0016 ,  H03K19/21

Abstract: Techniques are disclosed relating to dual-edge triggered (DET) clock gater circuitry. In some embodiments, an apparatus includes a first series of DET clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry. In some embodiments, ones of the DET clock gater circuits are controlled by respective control signals and are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock. In some embodiments, the apparatus also includes a first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode.

公开(公告)号：US20250015701A1

公开(公告)日：2025-01-09

申请号：US18893579

申请日：2024-09-23

Applicant: Apple Inc.

Inventor： Alexander B. Uan-Zo-li ,  Shuai Jiang ,  Jamie L. Langlinais ,  Per H. Hammarlund ,  Hans L. Yeager ,  Victor Zyuban ,  Sung J. Kim ,  Wei Xu ,  Rohan U. Mandrekar ,  Sambasivan Narayan ,  Mohamed H. Abu-Rahma ,  Jaroslav Raszka ,  Robert O. Bruckner

IPC: H02M1/00

Abstract: A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.

公开(公告)号：US20240235391A1

公开(公告)日：2024-07-11

申请号：US18153057

申请日：2023-01-11

Applicant: Apple Inc.

Inventor： Victor Zyuban ,  Jay B. Fletcher ,  Hao Zhou

IPC: H02M3/158

CPC classification number: H02M3/158

Abstract: A power management circuit for computer systems includes a power converter circuit that generates different voltage levels at different time periods. Multiple voltage regulator circuits are coupled to the output of the power converter circuit and to respective local power supply nodes. Switch devices are used to bypass the voltage regulator circuits during corresponding ones of the different time periods.

公开(公告)号：US20240063715A1

公开(公告)日：2024-02-22

申请号：US17820168

申请日：2022-08-16

Applicant: Apple Inc.

Inventor： Alexander B. Uan-Zo-li ,  Shuai Jiang ,  Jamie L. Langlinais ,  Per H. Hammarlund ,  Hans L. Yeager ,  Victor Zyuban ,  Sung J. Kim ,  Wei Xu ,  Rohan U. Mandrekar ,  Sambasivan Narayan ,  Mohamed H. Abu-Rahma ,  Jaroslav Raszka ,  Robert O. Bruckner

IPC: H02M3/07 ,  H02M1/00

CPC classification number: H02M3/07 ,  H02M1/0067

Abstract: A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.

公开(公告)号：US11320849B2

公开(公告)日：2022-05-03

申请号：US17006707

申请日：2020-08-28

Applicant: Apple Inc.

Inventor： Shawn Searles ,  Victor Zyuban ,  Mohamed Abu-Rahma

IPC: G05F1/575 ,  H03K17/22

Abstract: A voltage regulator circuit may generate a regulated voltage level using a voltage level of a feedback node. The regulated voltage level may be distributed, via a power distribution network, to package power supply node of a package, into which an integrated circuit has been mounted. Power switches included in the integrated circuit may couple the package power supply node to respective local power supply nodes in the integrated circuit. A particular power switch may selectively couple different ones of the local power supply nodes to the feedback node, allowing the voltage regulator circuit to compensate for reductions in the regulated voltage level due to the power distribution network, as well as adjust the regulated voltage level based on power consumptions of load circuits coupled to the local power supply nodes.