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    Technique for handling protocol conversion
    11.
    发明授权
    Technique for handling protocol conversion 有权

    公开(公告)号：US11537543B2

    公开(公告)日：2022-12-27

    申请号：US17189781

    申请日：2021-03-02

    Applicant: Arm Limited

    Inventor： Ashok Kumar Tummala ,  Jamshed Jalal ,  Antony John Harris ,  Jeffrey Carl Defilippi ,  Anitha Kona ,  Bruce James Mathewson

    IPC: G06F13/38 ,  G06F13/40

    Abstract: An apparatus and method are provided for handling protocol conversion. The apparatus has interconnect circuitry for routing messages between components coupled to the interconnect circuitry in a manner that conforms to a first communication protocol. Protocol conversion circuitry is coupled between the interconnect circuitry and an external communication path, for converting messages between the first communication protocol and a second communication protocol that has a layered architecture comprising multiple layers. The protocol conversion circuitry has a gateway component forming one of the components coupled to the interconnect circuitry, and a controller coupled with the gateway component and used to control connection with the external communication path. For a selected layer of the multiple layers, the protocol conversion circuitry provides, within the gateway component, upper selected layer circuitry to implement a first portion of functionality of the selected layer, where the first portion comprises at least protocol dependent functionality of the selected layer. It also provides, within the controller, lower selected layer circuitry to implement a remaining portion of the functionality of the selected layer, the remaining portion comprising only protocol independent functionality of the selected layer.

    Inter-chip communication in a multi-chip system
    15.
    发明授权
    Inter-chip communication in a multi-chip system 有权

    公开(公告)号：US10698825B1

    公开(公告)日：2020-06-30

    申请号：US16299291

    申请日：2019-03-12

    Applicant: Arm Limited

    Inventor： Gurunath Ramagiri ,  Ashok Kumar Tummala ,  Mark David Werkheiser ,  Jamshed Jalal ,  Premkishore Shivakumar ,  Paul Gilbert Meyer

    IPC: G06F12/00 ,  G06F12/0817 ,  G06F16/901

    Abstract: In a system-on-chip there is a local interconnect to connect local devices on the chip to one another, a gateway to connect the chip to a remote chip of a plurality of chips in a cache-coherent multi-chip system via an inter-chip interconnect, and a cache-coherent device. The cache-coherent device has a cache-coherency look-up table having entries for shared cache data lines. When a data access request is received via the inter-chip interconnect and the local interconnect a system-unique identifier for a request source of the data access request is generated in dependence on an inter-chip request source identifier used on the inter-chip interconnect and an identifier indicative of the remote chip. The bit-set used to express the system-unique identifier is larger than the bit-set used to express the inter-chip request source identifier. The system-unique identifier is used with respect to the cache-coherency look-up table to perform the cache-coherency actions for the cache line enabling more cache coherent devices to be supported.

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