公开(公告)号：US20210065839A1

公开(公告)日：2021-03-04

申请号：US16555964

申请日：2019-08-29

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Gaurav Rattan Singla

IPC: G11C29/00 ,  G11C11/4091 ,  G11C11/16 ,  G11C8/18

Abstract: Various implementations described herein are directed to a device having memory with an array of bitcells arranged in columns and rows, wherein a first number of columns represents a first number of output bits, and a second number of columns represents a second number of output bits. The device may include dummy wordline (DWL) circuitry having multiple DWL paths including a first DWL path disposed along the first number of columns and a second DWL path disposed along the second number of columns. The first DWL path has a shorter length than the second DWL path so as to allow for faster operation of the bitcells in the memory associated with the first number of output bits.

公开(公告)号：US20190244656A1

公开(公告)日：2019-08-08

申请号：US15891212

申请日：2018-02-07

Applicant: Arm Limited

Inventor： Yicong Li ,  Andy Wangkun Chen ,  Sharryl Renee Dettmer ,  Lalit Gupta ,  Jitendra Dasani ,  Yeon Jun Park ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC: G11C11/4097 ,  G11C7/18 ,  G11C11/419 ,  H01L27/11

Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.

公开(公告)号：US20190066770A1

公开(公告)日：2019-02-28

申请号：US15684255

申请日：2017-08-23

Applicant: ARM Limited

Inventor： Rajiv Kumar Sisodia ,  Navin Agarwal ,  Shri Sagar Dwivedi ,  Jitendra Dasani ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Daksheshkumar Maganbhai Malaviya

IPC: G11C11/419

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include read circuitry coupled to bitlines, and the read circuitry may be activated based on a read select signal to perform a read operation on the bitlines. The integrated circuit may include write circuitry coupled to the bitlines, and the write circuitry may be activated based on a write select signal to perform a write operation on the bitlines. The integrated circuit may include bitline discharge control circuitry coupled to the bitlines and the write circuitry, and the bitline discharge control circuitry may control the bitline discharge of the bitlines during the read operation so as to restrict a false read on the bitlines by providing a discharge boundary for the bitlines during the read operation.

公开(公告)号：US10147482B2

公开(公告)日：2018-12-04

申请号：US15462549

申请日：2017-03-17

Applicant: ARM Limited

Inventor： Jitendra Dasani ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC: G11C11/419 ,  G11C11/418

Abstract: A memory device includes a bitcell array having a plurality of bitcells, a dummy wordline, a dummy row cell pulldown, and a write tracker coupling the dummy wordline to the dummy row cell pulldown. The write tracker is configured as a transmission gate during a read operation on the bitcell array, and is configured as having only one or more active nMOSFETs during a write operation on the bitcell array.

公开(公告)号：US20180268894A1

公开(公告)日：2018-09-20

申请号：US15462549

申请日：2017-03-17

Applicant: ARM Limited

Inventor： Jitendra Dasani ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/227 ,  G11C11/418

Abstract: A memory device includes a bitcell array having a plurality of bitcells, a dummy wordline, a dummy row cell pulldown, and a write tracker coupling the dummy wordline to the dummy row cell pulldown. The write tracker is configured as a transmission gate during a read operation on the bitcell array, and is configured as having only one or more active nMOSFETs during a write operation on the bitcell array.

公开(公告)号：US09953701B1

公开(公告)日：2018-04-24

申请号：US15439899

申请日：2017-02-22

Applicant: ARM Limited

Inventor： Fakhruddin Ali Bohra ,  Lalit Gupta ,  Shri Sagar Dwivedi ,  Jitendra Dasani

IPC: G11C11/34 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: An SRAM with a first bitcell array having a first density and a first access speed, and a second bitcell array having a second density larger than the first density and a second access speed less than the first access speed. The SRAM further includes a first set of wordline drivers coupled to the first bitcell array, a second set of wordline drivers coupled to the second bitcell array, and a row decoder coupled to both the first and second bitcell arrays.

公开(公告)号：US09911510B1

公开(公告)日：2018-03-06

申请号：US15288832

申请日：2016-10-07

Applicant: ARM Limited

Inventor： Jungtae Kwon ,  Young Suk Kim ,  Vivek Nautiyal ,  Pranay Prabhat ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Satinderjit Singh ,  Lalit Gupta

IPC: G11C29/00 ,  G11C11/418 ,  G11C11/412

CPC classification number: G11C29/76 ,  G11C8/04 ,  G11C11/413 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit having a memory cell array with multiple rows of memory cells including at least one redundant row of memory cells. The memory cell array may be partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells and a second region of memory cells corresponding to a second part of the redundant row of memory cells. The integrated circuit may include wordline driver circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells. In some instances, the integrated circuit may include row shift circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells.

公开(公告)号：US20240005985A1

公开(公告)日：2024-01-04

申请号：US18369794

申请日：2023-09-18

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Vidit Babbar

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are related to a device having memory architecture having multiple bitcell arrays. The device may include column multiplexer circuitry coupled to the memory architecture via multiple bitlines for read access operations. The column multiplexer circuitry may perform read access operations in the multiple bitcell arrays via the bitlines based on a sense amplifier enable signal and a read multiplexer signal. The device may include control circuitry that provides the read multiplexer signal to the column multiplexer circuitry based on a clock signal and the sense amplifier enable signal so that the column multiplexer circuitry is able to perform the read access operations.

公开(公告)号：US11763880B2

公开(公告)日：2023-09-19

申请号：US16990951

申请日：2020-08-11

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Vidit Babbar

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are related to a device having memory architecture having multiple bitcell arrays. The device may include column multiplexer circuitry coupled to the memory architecture via multiple bitlines for read access operations. The column multiplexer circuitry may perform read access operations in the multiple bitcell arrays via the bitlines based on a sense amplifier enable signal and a read multiplexer signal. The device may include control circuitry that provides the read multiplexer signal to the column multiplexer circuitry based on a clock signal and the sense amplifier enable signal so that the column multiplexer circuitry is able to perform the read access operations.

公开(公告)号：US20210304816A1

公开(公告)日：2021-09-30

申请号：US16990951

申请日：2020-08-11

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Vidit Babbar

IPC: G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are related to a device having memory architecture having multiple bitcell arrays. The device may include column multiplexer circuitry coupled to the memory architecture via multiple bitlines for read access operations. The column multiplexer circuitry may perform read access operations in the multiple bitcell arrays via the bitlines based on a sense amplifier enable signal and a read multiplexer signal. The device may include control circuitry that provides the read multiplexer signal to the column multiplexer circuitry based on a clock signal and the sense amplifier enable signal so that the column multiplexer circuitry is able to perform the read access operations.