公开(公告)号：US20210065839A1

公开(公告)日：2021-03-04

申请号：US16555964

申请日：2019-08-29

申请人： Arm Limited

发明人： Lalit Gupta ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Gaurav Rattan Singla

IPC分类号： G11C29/00 ,  G11C11/4091 ,  G11C11/16 ,  G11C8/18

摘要： Various implementations described herein are directed to a device having memory with an array of bitcells arranged in columns and rows, wherein a first number of columns represents a first number of output bits, and a second number of columns represents a second number of output bits. The device may include dummy wordline (DWL) circuitry having multiple DWL paths including a first DWL path disposed along the first number of columns and a second DWL path disposed along the second number of columns. The first DWL path has a shorter length than the second DWL path so as to allow for faster operation of the bitcells in the memory associated with the first number of output bits.

公开(公告)号：US11043262B2

公开(公告)日：2021-06-22

申请号：US15886630

申请日：2018-02-01

申请人： Arm Limited

发明人： Arjunesh Namboothiri Madhavan ,  Akash Bangalore Srinivasa ,  Sujit Kumar Rout ,  Vikash ,  Gaurav Rattan Singla ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Jitendra Dasani ,  Lalit Gupta

IPC分类号： G11C11/419 ,  H01L29/94 ,  H01L27/11 ,  G11C7/10 ,  G11C7/18 ,  G11C8/16 ,  G11C7/12

摘要： Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.

公开(公告)号：US20200005836A1

公开(公告)日：2020-01-02

申请号：US16024449

申请日：2018-06-29

申请人： Arm Limited

发明人： Lalit Gupta ,  Fakhruddin Ali Bohra ,  Jitendra Dasani ,  Shri Sagar Dwivedi ,  Vivek Nautiyal ,  Gaurav Rattan Singla

IPC分类号： G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/14

摘要： Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.

公开(公告)号：US10943670B1

公开(公告)日：2021-03-09

申请号：US16555964

申请日：2019-08-29

申请人： Arm Limited

发明人： Lalit Gupta ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Gaurav Rattan Singla

IPC分类号： G11C7/14 ,  G11C5/06 ,  G11C8/14 ,  G11C29/00 ,  G11C11/4091 ,  G11C8/18 ,  G11C11/16

摘要： Various implementations described herein are directed to a device having memory with an array of bitcells arranged in columns and rows, wherein a first number of columns represents a first number of output bits, and a second number of columns represents a second number of output bits. The device may include dummy wordline (DWL) circuitry having multiple DWL paths including a first DWL path disposed along the first number of columns and a second DWL path disposed along the second number of columns. The first DWL path has a shorter length than the second DWL path so as to allow for faster operation of the bitcells in the memory associated with the first number of output bits.

公开(公告)号：US20190237135A1

公开(公告)日：2019-08-01

申请号：US15886630

申请日：2018-02-01

申请人： Arm Limited

发明人： Arjunesh Namboothiri Madhavan ,  Akash Bangalore Srinivasa ,  Sujit Kumar Rout ,  Vikash ,  Gaurav Rattan Singla ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Jitendra Dasani ,  Lalit Gupta

IPC分类号： G11C11/419 ,  H01L29/94 ,  H01L27/11 ,  G11C7/12 ,  G11C7/18 ,  G11C8/16 ,  G11C7/10

CPC分类号： G11C11/419 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/16 ,  H01L27/1116 ,  H01L29/94

摘要： Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.