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公开(公告)号：US20220197791A1
公开(公告)日：2022-06-23
申请号：US17130474
申请日：2020-12-22
Applicant: Arm Limited
Inventor： Alexander Donald Charles CHADWICK , Andrew Brookfield SWAINE , Gareth James EVANS , Jonathan Curtis BEARD
Abstract: An apparatus comprises memory access circuitry to access a memory system; a plurality of memory mapped registers, including at least an insert register and a producer pointer register; and control circuitry to perform an insert operation in response to receipt of an insert request from a requester device sharing access to the memory system. The insert request specifies an address mapped to the insert register and an indication of a payload. The insert operation includes controlling the memory access circuitry to write the payload to a location in the memory system selected based on a producer pointer value stored in the producer pointer register, and updating the producer pointer register to increment the producer pointer value.
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公开(公告)号：US20200034230A1
公开(公告)日：2020-01-30
申请号：US16043975
申请日：2018-07-24
Applicant: Arm Limited
Inventor： Reiley JEYAPAUL , Roxana RUSITORU , Jonathan Curtis BEARD
Abstract: A memory system for a data processing apparatus includes a fault management unit, a memory controller (such as a memory management unit or memory node controller), and one or more storage devices accessible via the memory controller and configured for storing critical data. The fault management unit detects and corrects a fault in the stored critical data, a storage device or the memory controller. A data fault may be corrected using a copy of the data, or an error correction code, for example. A level of failure protection for the critical data, such as a number of copies, an error correction code or a storage location in the one or more storage devices, is determined dependent upon a failure characteristic of the device. A failure characteristic, such as an error rate, may be monitored and updated dynamically.
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Patent Agency Ranking
公开(公告)号：US20210306414A1
公开(公告)日：2021-09-30
申请号：US16828207
申请日：2020-03-24
Applicant: Arm Limited
Inventor： Jonathan Curtis BEARD , Jamshed JALAL , Curtis Glenn DUNHAM , Roxana RUSITORU
Abstract: Circuitry comprises a set of data handling nodes comprising: two or more master nodes each having respective storage circuitry to hold copies of data items from a main memory, each copy of a data item being associated with indicator information to indicate a coherency state of the respective copy, the indicator information being configured to indicate at least whether that copy has been updated more recently than the data item held by the main memory; a home node to serialise data access operations and to control coherency amongst data items held by the set of data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; and one or more slave nodes including the main memory; in which: a requesting node of the set of data handling nodes is configured to communicate a conditional request to a target node of the set of data handling nodes in respect of a copy of a given data item at a given memory address, the conditional request being associated with an execution condition and being a request that the copy of the given data item is written to a destination node of the data handling nodes; and the target node is configured, in response to the conditional request: (i) when the outcome of the execution condition is successful, to write the data item to the destination node and to communicate a completion-success indicator to the requesting node; and (ii) when the outcome of the execution condition is a failure, to communicate a completion-failure indicator to the requesting node.
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公开(公告)号：US20180150315A1
公开(公告)日：2018-05-31
申请号：US15361770
申请日：2016-11-28
Applicant: ARM Limited
Inventor： Curtis Glenn DUNHAM , Jonathan Curtis BEARD , Roxana RUSITORU
Abstract: Data processing apparatus comprises one or more interconnected processing elements; each processing element being configured to execute processing instructions of program tasks; each processing element being configured to save context data relating to a program task following execution of that program task by that processing element; and to load context data, previously saved by that processing element or another of the processing elements, at resumption of execution of a program task; each processing element having respective associated format definition data to define one or more sets of data items for inclusion in the context data; the apparatus comprising format selection circuitry to communicate the format definition data of each of the processing elements with others of the processing elements and to determine, in response to the format definition data for each of the processing elements, a common set of data items for inclusion in the context data.
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公开(公告)号：US20180150243A1
公开(公告)日：2018-05-31
申请号：US15361843
申请日：2016-11-28
Applicant: ARM Limited
Inventor： Jonathan Curtis BEARD
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/065 , G06F3/0659 , G06F3/067 , G06F12/02 , G06F12/0284 , G06F12/0607 , G06F12/0804 , G06F12/0811 , G06F12/10 , G06F2212/1016 , G06F2212/657
Abstract: A memory system of a data processing system includes one or more storage devices and a data rearrangement engine for moving data between memory regions of the plurality of memory regions. The data rearrangement engine is configured to rearrange data stored at non-contiguous addresses in a source memory region into contiguous address in a destination region responsive to a rearrangement specified by a host processing unit of the data processing system. A description of the rearranged data is maintained in a metadata memory region. Rearranged data may be accessed by one or more host processing units. Write-back of data from the destination to the source region may be reduced by use of Bloom filter or the like.
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公开(公告)号：US20170344367A1
公开(公告)日：2017-11-30
申请号：US15166467
申请日：2016-05-27
Applicant: ARM Limited
Inventor： Jonathan Curtis BEARD , Wendy ELSASSER , Shibo WANG
IPC: G06F9/30 , G06F12/0875 , G06F9/32 , G06F12/084
Abstract: A data processing apparatus includes a multi-level memory system, one or more first processing unit coupled to the memory system at a first level and one or more second processing units each coupled to the memory system at a second level. A first reorder buffer maintains data order during execution of instructions by the first and second processing units and a second reorder buffer maintains data order during execution of the instructions by an associated second processing unit. An entry in the first reorder buffer is configured, dependent upon an indicator bit, as an entry for a single instruction or a pointer to an entry in the second reorder buffer. An entry in the second reorder buffer includes instruction block start and end addresses and indicators of input and output register. Instructions are released to a processing unit when all inputs, as indicated by the reorder buffers, are available.
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公开(公告)号：US20170344366A1
公开(公告)日：2017-11-30
申请号：US15166444
申请日：2016-05-27
Applicant: ARM Limited
Inventor： Jonathan Curtis BEARD , Wendy ELSASSER , Eric VAN HENSBERGEN , Stephan DIESTELHORST
IPC: G06F9/30 , G06F9/38 , G06F12/084 , G06F12/0875 , G06F12/0897
Abstract: A data processing apparatus, and method of operation thereof, for executing instructions. The apparatus includes one or more host processors, each having a first processing unit, and a multi-level memory system. One or more levels of the memory system are tightly coupled to a corresponding second processing unit. At least one of the host processors includes an instruction scheduler that routes instructions selectively to at least one of the first and second processing units, dependent upon the availability of the processing units and the location, within the memory system, of data to be used when executing the instructions.
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