公开(公告)号：US20180253309A1

公开(公告)日：2018-09-06

申请号：US15759900

申请日：2016-09-14

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS

IPC: G06F9/30 ,  G06F9/32

CPC classification number: G06F9/30036 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/325 ,  G06F9/345 ,  G06F9/3555

Abstract: A vector data transfer instruction is provided for triggering a data transfer between storage locations corresponding to a contiguous block of addresses and multiple data elements of at least one vector register. The instruction specifies a start address of the contiguous block using a base register and an immediate offset value specifies as a multiple of the size of the contiguous block of addresses. This is useful for loop unrolling which can help to improve performance of vectorised code by combining multiple iterations of a loop into a single iteration of an unrolled loop, to reduce the loop control overhead.

公开(公告)号：US20180203699A1

公开(公告)日：2018-07-19

申请号：US15741551

申请日：2016-06-21

Applicant: ARM Limited

Inventor： Nigel John STEPHENS

IPC: G06F9/30

CPC classification number: G06F9/30149 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/30192 ,  G06F9/3861

Abstract: A data processing system (2) includes processing circuitry (18) and decoder circuitry (14) for decoding program instructions and controlling the processor circuitry. The decoder circuitry is responsive to a vector operand bit size dependant instruction executed within a selected exception level state of a hierarchy of exception level states to control the processing circuitry to perform processing with a vector operand bit size governed by a limiting value of the vector operand bit size associated with the currently selected exception level state, any programmable limit value set for an exception level state closer to a top exception level state within the hierarchy and the implemented limit.

公开(公告)号：US20170329603A1

公开(公告)日：2017-11-16

申请号：US15666978

申请日：2017-08-02

Applicant: ARM Limited

Inventor： Simon John CRASKE ,  Richard Roy GRISENTHWAITE ,  Nigel John STEPHENS

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30003 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3842

Abstract: An apparatus performs an operation on a register, and then conditionally selects either that register or a further register on which no operation has been performed. The apparatus includes a decoder that decodes a conditional select instruction that specifies a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. A data processor is responsive to the decoded conditional select instruction and the condition (i) having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register, and (ii) not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

公开(公告)号：US20170153891A1

公开(公告)日：2017-06-01

申请号：US15431955

申请日：2017-02-14

Applicant: ARM Limited

Inventor： David James SEAL ,  Richard Roy GRISENTHWAITE ,  Nigel John STEPHENS

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30167 ,  G06F7/764 ,  G06F7/768 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3887

Abstract: A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.

公开(公告)号：US20200319885A1

公开(公告)日：2020-10-08

申请号：US16650999

申请日：2018-11-15

Applicant: Arm Limited

Inventor： Mbou EYOLE ,  Nigel John STEPHENS ,  Neil BURGESS ,  Grigorios MAGKLIS

IPC: G06F9/30 ,  G06F7/50

Abstract: Vector add-with-carry instructions are described which use some elements of a destination vector register, or corresponding fields of a predicate register, to provide the carry information corresponding to results of an add-with-carry operation. This is useful for accelerating computations involving multiplications of long integer values.

公开(公告)号：US20190088307A1

公开(公告)日：2019-03-21

申请号：US15711116

申请日：2017-09-21

Applicant: ARM LIMITED

Inventor： Neil BURGESS ,  Nigel John STEPHENS ,  Lee Evan EISEN ,  Jaime FERRAGUT MARTINEZ-VARA DE REY

IPC: G11C11/4094 ,  G11C11/56

CPC classification number: G11C11/4094 ,  G06F9/30 ,  G11C7/1006 ,  G11C11/5621 ,  G11C19/28 ,  G11C19/38

Abstract: Circuitry comprises: a set of bit processing circuitries to apply two or more successive instances of bitwise processing to an ordered bit array; each bit processing circuitry for a given bit position within the ordered bit array comprising: bit shifting circuitry to selectively apply a bit shift of a respective input bit to a next bit processing circuitry in a first direction relative to the ordered bit array, in response to an active state of a bit shift control signal, the bit shifting circuitry not applying the bit shift in response to an inactive state of the bit shift control signal; and bit shift control circuitry to selectively allow or inhibit a bit shifting operation in response to one or more inhibit control signals; in which: the bit shift control circuitry is configured to selectively propagate an output inhibit control signal, indicating that a bit shifting operation should be inhibited, as an inhibit control signal to bit processing circuitry applying a next instance of the bitwise processing at the given bit position, in dependence upon the bit shift control signal and the one or more inhibit control signals.

公开(公告)号：US20190026173A1

公开(公告)日：2019-01-24

申请号：US16070592

申请日：2016-12-15

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS

IPC: G06F11/07 ,  G06F9/30 ,  G06F9/38

Abstract: Processing circuitry (85) supports a vector atomic memory update instruction identifying an address vector, for triggering at least one atomic memory update operation for performing an atomic memory update to a memory location having an address determined based on a corresponding active data element of the address vector. When a fault condition is determined for the address determined using a given faulting active data element of the address vector, atomic memory update operations for that element and any subsequent element in a predetermined sequence are suppressed. If the faulting element is the first active data element in the sequence, a fault handling response is triggered, while otherwise the fault handling response is suppressed and status information is stored indicating which element is the faulting element.

公开(公告)号：US20190012176A1

公开(公告)日：2019-01-10

申请号：US15748734

申请日：2016-07-28

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  Grigorios MAGKLIS ,  Alejandro MARTINEZ VICENTE ,  Nathanael PREMILLIEU ,  Mbou EYOLE

IPC: G06F9/30

CPC classification number: G06F9/30149 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/3836

Abstract: Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of a data vector comprising a plurality of data items at respective positions in the data vector, according to the state of respective predicate flags associated with the positions; the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a WHILE instruction and a CHANGE instruction, to control the instruction processing dependent upon a number of the predicate flags.

公开(公告)号：US20180267798A1

公开(公告)日：2018-09-20

申请号：US15761476

申请日：2016-09-14

Applicant: ARM LIMITED

Inventor： Richard Roy GRISENTHWAITE ,  Nigel John STEPHENS

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus 2 has instruction fusing circuitry 50 for fusing two or more instructions fetched from a data store to generate a fused instruction to be processed by processing circuitry 14. A move prefix instruction is provided which indicates to the instruction fusing circuitry 50 that the move prefix instruction can be fused with an immediately following data processing instruction without needing to compare registers specified by the move prefix instruction and the immediately following instruction. This enables the instruction fusing circuitry 50 to be implemented with reduced hardware and energy cost.

公开(公告)号：US20180203692A1

公开(公告)日：2018-07-19

申请号：US15743745

申请日：2016-06-23

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS

IPC: G06F9/30 ,  G06F17/16

CPC classification number: G06F9/30014 ,  G06F9/30036 ,  G06F17/16

Abstract: A data processing system (2) supports vector processing operations performed upon vector operands comprising a plurality of vector operand elements. The data processing system includes a processor (4) having an instruction decoder (14) which decodes mixed-element-sized vector arithmetic instructions to generate control signals (16) which control processing circuitry (18) to perform arithmetic operations upon a first vector of first source operand elements ai of a first bit size A, and a second vector of second source operand elements bj of a second bit size B. The second bit size B is greater than the first bit size A.