Preparing and executing command streams in data processing systems

    公开(公告)号:US10861125B2

    公开(公告)日:2020-12-08

    申请号:US16402031

    申请日:2019-05-02

    Applicant: Arm Limited

    Abstract: When a processing resource of a data processing system is to perform processing tasks for applications executing on a host processor, the host processor prepares a plurality of command streams to cause the processing resource to perform the processing tasks. When a processing task to be added to a command stream has a dependency on a processing task or tasks that will be included in another command stream, a wait command is added to the command stream that is to include the processing task that has a dependency on a processing task or tasks that will be included in the another command stream, to cause the processing resource to delay executing subsequent commands in the command stream after the wait command, until the processing resource has reached a particular position in the another command stream.

    Graphics processing
    12.
    发明授权

    公开(公告)号:US10255718B2

    公开(公告)日:2019-04-09

    申请号:US15393120

    申请日:2016-12-28

    Applicant: ARM Limited

    Abstract: A graphics processing pipeline includes position shading circuitry, a tiler, varying-only vertex shading circuitry and fragment (frontend) shading circuitry. The tiler reads a list of indices defining a set of vertices to be processed by the graphics processing pipeline and determines whether or not vertex shading is required for the positional attributes of the vertices. If vertex shading is required, the tiler sends a position shading request for the vertices to the position shading circuitry. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output and that accordingly should be subjected to a second, varying shading, vertex shading operation. When the tiler determines that a vertex (or group of vertices) should be subjected to the second, varying shading, vertex shading operation, the tiler sends a varying shading request for the vertex (or vertices) to the varying shading circuitry.

    GRAPHICS PROCESSING SYSTEMS
    14.
    发明申请
    GRAPHICS PROCESSING SYSTEMS 有权
    图形处理系统

    公开(公告)号:US20160239939A1

    公开(公告)日:2016-08-18

    申请号:US15042540

    申请日:2016-02-12

    Applicant: ARM Limited

    CPC classification number: G06T15/005 G06T11/40

    Abstract: In a graphics processing system, a driver for the graphics processing pipeline can include conditional graphics processing tasks in the graphics processing tasks that are to be executed by the graphics processing pipeline to generate a render output required by an application. Each such conditional task has associated with it a condition to be used by the graphics processing pipeline to determine whether to execute processing for the task or not and a region of the render output over which the processing for the task will be executed when the condition for the task is met. The graphics processing pipeline determines whether the condition associated with the task has been met, and only executes the processing for the task if the condition associated with the task has been met.

    Abstract translation: 在图形处理系统中,用于图形处理流水线的驱动器可以包括由图形处理流水线执行的图形处理任务中的条件图形处理任务,以生成应用所需的渲染输出。 每个这样的条件任务已经与它相关联地被图形处理流水线使用的条件来确定是否执行任务的处理,以及渲染输出的区域,当该条件为 任务得到满足。 图形处理流水线确定是否满足与任务相关联的条件,并且只有在满足与任务相关联的条件的情况下才执行该任务的处理。

    Graphics Processors
    15.
    发明公开
    Graphics Processors 审中-公开

    公开(公告)号:US20240169663A1

    公开(公告)日:2024-05-23

    申请号:US17989548

    申请日:2022-11-17

    Applicant: Arm Limited

    CPC classification number: G06T15/405 G06T15/005

    Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information indicates which primitives should be rendered for which sampling positions of the render output.

    GRAPHICS PROCESSORS
    16.
    发明公开
    GRAPHICS PROCESSORS 审中-公开

    公开(公告)号:US20240169619A1

    公开(公告)日:2024-05-23

    申请号:US18509687

    申请日:2023-11-15

    Applicant: Arm Limited

    CPC classification number: G06T11/40 G06T1/20

    Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence, the visibility information being usable to determine whether fragments for a primitive in the sequence should subsequently be processed further, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information indicates which primitives should be rendered for which sampling positions of the render output in a hierarchical manner.

    Control of instruction execution in a data processor

    公开(公告)号:US10824468B2

    公开(公告)日:2020-11-03

    申请号:US16273448

    申请日:2019-02-12

    Applicant: Arm Limited

    Abstract: A method of controlling a data processor to perform data processing operations is disclosed in which a host processor prepares one or more queue(s) of operations for execution by the data processor. When an error is encountered in the processing of an operation for one of the one or more queue(s), a queue can be set into an error state in which instructions that may have a data dependency on another operation are not executed. The host processor includes in the queues error barrier instructions that divide the respective queues into sets of operations between which there are no data processing dependencies. An error state for a queue can thus be cleared when its processing reaches the next error barrier instruction in the queue.

    Graphics processing systems using a subset of pipeline stages

    公开(公告)号:US10803547B2

    公开(公告)日:2020-10-13

    申请号:US15804784

    申请日:2017-11-06

    Applicant: Arm Limited

    Abstract: In a graphics processing system, an application executing on a host processor can request graphics processing operations that are to be performed by only subsets of the set of stages of a graphics processing pipeline implemented by a graphics processor. In response to such a request, the driver for the graphics processor causes the graphics processing operation that is to be performed using only a subset of the set of stages of the graphics processing pipeline to be performed. The driver can cause the graphics processing operation that is to be performed by the subset of stages of the graphics processing pipeline to be performed by the graphics processor, or on the host processor.

    Method and apparatus for graphics processing of a graphics fragment

    公开(公告)号:US09965876B2

    公开(公告)日:2018-05-08

    申请号:US13845604

    申请日:2013-03-18

    Applicant: ARM Limited

    CPC classification number: G06T11/40

    Abstract: A graphics processing pipeline determines whether respective graphics processing operations, such as respective blends, respective depth tests, etc., to be performed at a stage of the graphics processing pipeline would produce the same result for each sampling point of a set of plural sampling points represented by a fragment being processed by the graphics processing pipeline. If it is determined that respective graphics processing operations would produce the same result for each of the sampling points, then only a single instance of the graphics processing operation is performed and the result of that graphics processing operation is associated with each of the sampling points. The number of instances of the graphics processing operations needed to process the set of plural sampling points which the fragment represents is reduced in comparison to conventional multisampling graphics processing techniques which perform graphics processing operations for fragments on a “per sample” basis. The determination of whether or not the same result would be produced for each sampling point of the set of plural sampling points is facilitated by providing metadata which indicates whether or not fragment data and/or stored sample data for use when processing the sampling points is the same.

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