公开(公告)号：US10795820B2

公开(公告)日：2020-10-06

申请号：US15427435

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Tushar P Ringe

IPC: G06F12/0831 ,  G06F11/14

Abstract: Apparatus and a corresponding method of operating the apparatus, in a coherent interconnect system comprising a requesting master device and a data-storing slave device, are provided. The apparatus maintains records of coherency protocol transactions received from the requesting master device whilst completion of the coherency protocol transactions are pending and is responsive to reception of a read transaction from the requesting master device for a data item stored in the data-storing slave device to issue a direct memory transfer request to the data-storing slave device. A read acknowledgement trigger is added to the direct memory transfer request and in response to reception of a read acknowledgement signal from the data-storing slave device a record created by reception of the read transaction is updated corresponding to completion of the direct memory transfer request. The lifetime that the apparatus needs to maintain the record is thus reduced, despite the read transaction being satisfied by a direct memory transfer. A corresponding data-storing slave device and method of operating the data-storing slave device are also provided.

公开(公告)号：US12079132B2

公开(公告)日：2024-09-03

申请号：US18101806

申请日：2023-01-26

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Ashok Kumar Tummala ,  Wenxuan Zhang ,  Daniel Thomas Pinero ,  Tushar P Ringe

IPC: G06F12/00 ,  G06F12/0888

CPC classification number: G06F12/0888 ,  G06F2212/1024

Abstract: Data transfer between caching domains of a data processing system is achieved by a local coherency node (LCN) of a first caching domain receiving a read request for data associated with a second caching domain, from a requesting node of the first caching domain. The LCN requests the data from the second caching domain via a transfer agent. In response to receiving a cache line containing the data from the second caching domain, the transfer agent sends the cache line to the requesting node, bypassing the LCN and, optionally, sends a read-receipt indicating the state of the cache line to the LCN. The LCN updates a coherency state for the cache line in response to receiving the read-receipt from the transfer agent and a completion acknowledgement from the requesting node. Optionally, the transfer agent may send the cache line via the LCN when congestion is detected in a response channel of the data processing system.

公开(公告)号：US20240273025A1

公开(公告)日：2024-08-15

申请号：US18109453

申请日：2023-02-14

Applicant: Arm Limited

Inventor： Wenxuan Zhang ,  Jamshed Jalal ,  Mark David Werkheiser ,  Sakshi Verma ,  Ritukar Khanna ,  Devi Sravanthi Yalamarthy ,  Gurunath Ramagiri ,  Mukesh Patel ,  Tushar P Ringe

IPC: G06F12/0831 ,  G06F12/0871

CPC classification number: G06F12/0833 ,  G06F12/0871

Abstract: A super home node of a first chip of a multi-chip data processing system manages coherence for both local and remote cache lines accessed by local caching agents and local cache lines accessed by caching agents of one or more second chips. Both local and remote cache lines are stored in a shared cache, and requests are stored in shared point-of-coherency queue. An entry in a snoop filter table of the super home node includes a presence vector that indicates the presence of a remote cache line at specific caching agents of the first chip or the presence of a local cache line at specific caching agents of the first chip and any caching agent of the second chip. All caching agents of the second chip are represented as a single caching agent in the presence vector.

公开(公告)号：US11599467B2

公开(公告)日：2023-03-07

申请号：US17331806

申请日：2021-05-27

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Bruce James Mathewson ,  Tushar P Ringe ,  Sean James Salisbury ,  Antony John Harris

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0895

Abstract: The present disclosure advantageously provides a system cache and a method for storing coherent data and non-coherent data in a system cache. A transaction is received from a source in a system, the transaction including at least a memory address, the source having a location in a coherent domain or a non-coherent domain of the system, the coherent domain including shareable data and the non-coherent domain including non-shareable data. Whether the memory address is stored in a cache line is determined, and, when the memory address is not determined to be stored in a cache line, a cache line is allocated to the transaction including setting a state bit of the allocated cache line based on the source location to indicate whether shareable or non-shareable data is stored in the allocated cache line, and the transaction is processed.

公开(公告)号：US20220382679A1

公开(公告)日：2022-12-01

申请号：US17331806

申请日：2021-05-27

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Bruce James Mathewson ,  Tushar P Ringe ,  Sean James Salisbury ,  Antony John Harris

IPC: G06F12/0815 ,  G06F12/0895

Abstract: The present disclosure advantageously provides a system cache and a method for storing coherent data and non-coherent data in a system cache. A transaction is received from a source in a system, the transaction including at least a memory address, the source having a location in a coherent domain or a non-coherent domain of the system, the coherent domain including shareable data and the non-coherent domain including non-shareable data. Whether the memory address is stored in a cache line is determined, and, when the memory address is not determined to be stored in a cache line, a cache line is allocated to the transaction including setting a state bit of the allocated cache line based on the source location to indicate whether shareable or non-shareable data is stored in the allocated cache line, and the transaction is processed.

公开(公告)号：US11431649B1

公开(公告)日：2022-08-30

申请号：US17214028

申请日：2021-03-26

Applicant: Arm Limited

Inventor： Mukesh Patel ,  Jamshed Jalal ,  Gurunath Ramagiri ,  Tushar P Ringe ,  Mark David Werkheiser

IPC: G06F13/20 ,  G06F13/42 ,  G06F12/0888 ,  G06F15/173 ,  H04L47/80 ,  H04L47/78 ,  H04L47/62 ,  H04L47/762

Abstract: The present disclosure advantageously provides a method and system for allocating shared resources for an interconnect. A request is received at a home node from a request node over an interconnect, where the request represents a beginning of a transaction with a resource in communication with the home node, and the request has a traffic class defined by a user-configurable mapping based on one or more transaction attributes. The traffic class of the request is determined. A resource capability for the traffic class is determined based on user configurable traffic class-based resource capability data. Whether a home node transaction table has an available entry for the request is determined based on the resource capability for the traffic class.

公开(公告)号：US11256646B2

公开(公告)日：2022-02-22

申请号：US16685082

申请日：2019-11-15

Applicant: Arm Limited

Inventor： Tushar P Ringe ,  Jamshed Jalal ,  Gurunath Ramagiri ,  Ashok Kumar Tummala ,  Mark David Werkheiser

IPC: G06F13/40 ,  G06F9/46

Abstract: An apparatus and method are provided for handling ordered transactions. The apparatus has a plurality of completer elements to process transactions, a requester element to issue a sequence of ordered transactions, and an interconnect providing, for each completer element, a communication channel between that completer element and the requester element for transfer of signals between that completer element and the requester element in either direction. A given completer element that is processing a given transaction in the sequence is arranged to issue a response signal to the requester element over its associated communication channel that comprises an ordered channel indication to identify whether the associated communication channel has an ordered channel property. The ordered channel property guarantees that processing of transactions issued by the requester element over the associated communication channel in a given order will be completed by the given completer element in the same given order. The requester element is then responsive to the ordered channel indication to control timing of issuance from the requester element of at least one signal relating to one or more transactions after the given transaction in the sequence. By such an approach, the ordering flow adopted for ordered transactions can be varied by the requester element in dependence on the presence or absence of an ordered channel, whilst enabling interconnect-agnostic requester element designs to be utilised.

公开(公告)号：US11074206B1

公开(公告)日：2021-07-27

申请号：US17036225

申请日：2020-09-29

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Tushar P Ringe ,  Kishore Kumar Jagadeesha ,  Ashok Kumar Tummala ,  Rishabh Jain ,  Devi Sravanthi Yalamarthy

IPC: G06F13/28 ,  G06F13/40 ,  G06F9/46

Abstract: The present disclosure advantageously provides a method and system for transferring data over at least one interconnect. A request node, coupled to an interconnect, receives a first write burst from a first device over a first connection, divides the first write burst into an ordered sequence of smaller write requests based on the size of the first write burst, and sends the ordered sequence of write requests to a home node coupled to the interconnect. The home node generates an ordered sequence of write transactions based on the ordered sequence of write requests, and sends the ordered sequence of write transactions to a write combiner coupled to the home node. The write combiner combines the ordered sequence of write transactions into a second write burst that is the same size as the first write burst, and sends the second write burst to a second device over a second connection.

公开(公告)号：US20210126877A1

公开(公告)日：2021-04-29

申请号：US17051028

申请日：2019-05-02

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Tushar P Ringe ,  Phanindra Kumar Mannava ,  Dimitrios Kaseridis

IPC: H04L12/931 ,  G06F13/36 ,  H04L12/801 ,  H04L12/933 ,  H04L12/947

Abstract: An improved protocol for data transfer between a request node and a home node of a data processing network that includes a number of devices coupled via an interconnect fabric is provided that minimizes the number of response messages transported through the interconnect fabric. When congestion is detected in the interconnect fabric, a home node sends a combined response to a write request from a request node. The response is delayed until a data buffer is available at the home node and home node has completed an associated coherence action. When the request node receives a combined response, the data to be written and the acknowledgment are coalesced in the data message.