公开(公告)号：US20240126554A1

公开(公告)日：2024-04-18

申请号：US17965275

申请日：2022-10-13

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  ABHISHEK RAJA ,  Zachary Allen KINGSBURY

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/384 ,  G06F9/3842

Abstract: A data processing apparatus is provided. Decode circuitry decodes a stream of instructions including a store instruction and a load instruction. Prediction circuitry predicts that the load instruction loads data from memory that is stored to the memory by the store instruction and the prediction is based on a hash of a program counter value of the store instruction.

公开(公告)号：US20220357953A1

公开(公告)日：2022-11-10

申请号：US17315737

申请日：2021-05-10

Applicant: Arm Limited

Inventor： Jaekyu LEE ,  Yasuo ISHII ,  Krishnendra NATHELLA ,  Dam SUNWOO

IPC: G06F9/38 ,  G06F9/30

Abstract: A data processing apparatus is provided. It includes control flow detection prediction circuitry that performs a presence prediction of whether a block of instructions contains a control flow instruction. A fetch queue stores, in association with prediction information, a queue of indications of the instructions and the prediction information comprises the presence prediction. An instruction cache stores fetched instructions that have been fetched according to the fetch queue. Post-fetch correction circuitry receives the fetched instructions prior to the fetched instructions being received by decode circuitry, the post-fetch correction circuitry includes analysis circuitry that causes the fetch queue to be at least partly flushed in dependence on a type of a given fetched instruction and the prediction information associated with the given fetched instruction.

公开(公告)号：US20220156078A1

公开(公告)日：2022-05-19

申请号：US16952661

申请日：2020-11-19

Applicant: Arm Limited

Inventor： Joseph Michael PUSDESRIS ,  Yasuo ISHII ,  Eric Charles QUINNELL ,  Nicholas Andrew PLANTE

IPC: G06F9/38 ,  G06F9/30

Abstract: In register renaming circuitry architectural registers specified in instructions are mapped to physical registers using a mapping table. Operations to be performed with respect to the physical registers are generated in dependence on the instructions and on the mapping table entries. When the mapping table has a mapping of a first instruction destination physical register for a first instruction destination architectural register specified in a first instruction, a second instruction specifying the first instruction destination architectural register as a second instruction source architectural register causes an adapted second operation to be generated corresponding to the second instruction using at least one first instruction source physical register as at least one second instruction source physical register. The adapted second operation incorporates a first operation corresponding to the first instruction.

公开(公告)号：US20210089472A1

公开(公告)日：2021-03-25

申请号：US16577271

申请日：2019-09-20

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Thibaut Elie LANOIS ,  Houdhaifa BOUZGUARROU

IPC: G06F12/121 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/30

Abstract: An apparatus comprises a cache comprising cache entries, each cache entry storing cached information and an entry usefulness value indicative of usefulness of the cached information. Base usefulness storage circuitry stores a base usefulness value. Cache replacement control circuitry controls, based on a usefulness level determined for a given cache entry, whether the given cache entry is selected for replacement. The cache replacement control circuitry determines the usefulness level for the given cache entry based on a difference between the entry usefulness value specified by the given cache entry and the base usefulness value stored in the base usefulness storage circuitry.

公开(公告)号：US20210056034A1

公开(公告)日：2021-02-25

申请号：US16549291

申请日：2019-08-23

Applicant: Arm Limited

Inventor： Joseph Michael PUSDESRIS ,  Yasuo ISHII

IPC: G06F12/0891 ,  G06F9/30 ,  G06F12/0875

Abstract: A data processing apparatus is provided. It includes cache circuitry to store a plurality of items, each having an associated indicator. Processing circuitry executes instructions using at least some of the plurality of items. Fill circuitry inserts a new item into the cache circuitry. Eviction circuitry determines which of the plurality of items is to be a victim item based on the indicator, and evicts the victim item from the cache circuitry. Detection circuitry detects a state of the processing circuitry at a time that the new item is inserted into the cache circuitry, and sets the indicator in dependence on the state.

公开(公告)号：US20200073666A1

公开(公告)日：2020-03-05

申请号：US16120674

申请日：2018-09-04

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Muhammad Umar FAROOQ ,  Chris ABERNATHY

IPC: G06F9/38

Abstract: Branch prediction circuitry processes blocks of instructions and provides instruction fetch circuitry with indications of predicted next blocks of instructions to be retrieved from memory. Main branch target storage stores branch target predictions for branch instructions in the blocks of instructions. Secondary branch target storage caches the branch target predictions from the main branch target storage. Look-ups in the secondary branch target storage and the main branch target storage are performed in parallel. The main branch target storage is set-associative and an entry in the main branch target storage comprises multiple ways, wherein each way of the multiple ways stores a branch target prediction for one branch instruction. The branch prediction circuitry stores a way prediction for which of the multiple ways contain the branch target predictions for a predicted next block of instructions and stores a flag associated with the way prediction indicating whether all branch target predictions stored for the predicted next block of instructions in the main branch target storage are also stored in the secondary branch target storage. An active value of the flag suppresses the look-up in the main branch target storage for the predicted next block of instructions.

公开(公告)号：US20250028531A1

公开(公告)日：2025-01-23

申请号：US18353345

申请日：2023-07-17

Applicant: Arm Limited

Inventor： Alexander Cole SHULYAK ,  Yasuo ISHII ,  Joseph Michael PUSDESRIS

IPC: G06F9/30 ,  G06F13/16

Abstract: Processing circuitry to execute load operations, each associated with an identifier. Prediction circuitry to receive a given load value associated with a given identifier, and to make, in dependence on the given load value, a prediction indicating a predicted load value for a subsequent load operation to be executed by the processing circuitry and an ID-delta value indicating a difference between the given identifier and an identifier of the subsequent load operation. The predicted load value being predicted in dependence on at least one occurrence of each of the given load value and the predicted load value during execution of a previously-executed sequence of load operations. The prediction circuitry is configured to determine the ID-delta value in dependence on a difference between identifiers associated with the at least one occurrence of each of the given load value and the predicted load value in the previously-executed sequence of load operations.

公开(公告)号：US20240370266A1

公开(公告)日：2024-11-07

申请号：US18312052

申请日：2023-05-04

Applicant: Arm Limited

Inventor： Alexander Cole SHULYAK ,  Yasuo ISHII ,  Dam SUNWOO ,  Houdhaifa BOUZGUARROU

IPC: G06F9/38 ,  G06F12/0875

Abstract: An apparatus is provided having pointer storage to store pointer values for a plurality of pointers, with the pointer values of the pointers being differentially incremented in response to a series of increment events. Tracker circuitry maintains a plurality of tracker entries, each tracker entry identifying a control flow instruction and a current active pointer (from amongst the pointers) to be associated with that control flow instruction. Cache circuitry maintains a plurality of cache entries, each cache entry storing a resolved behaviour of an instance of a control flow instruction identified by a tracker entry along with an associated tag value generated when the resolved behaviour was allocated into that cache entry. For a given entry the associated tag value may be generated in dependence on an address indication of the control flow instruction whose resolved behaviour is being stored in that entry and the current active pointer associated with that control flow instruction. Prediction circuitry is responsive to a prediction trigger associated with a replay of a given instance of a given control flow instruction identified by a tracker entry, to cause a lookup operation to be performed by the cache circuitry using a comparison tag value generated in dependence on the address indication of the given control flow instruction and the current active pointer. In the event of a hit being detected in a given cache entry, the resolved behaviour stored in the given cache entry is used as the predicted behaviour of the given instance of the given control flow instruction, provided a prediction confidence metric is met.

公开(公告)号：US20230176979A1

公开(公告)日：2023-06-08

申请号：US17541007

申请日：2021-12-02

Applicant: Arm Limited

Inventor： Alexander Cole SHULYAK ,  Joseph Michael PUSDESRIS ,  . ABHISHEK RAJA ,  Karthik SUNDARAM ,  Anoop Ramachandra IYER ,  Michael Brian SCHINZLER ,  James David DUNDAS ,  Yasuo ISHII

IPC: G06F12/1027

CPC classification number: G06F12/1027

Abstract: An apparatus comprises memory management circuitry to perform a translation table walk for a target address of a memory access request and to signal a fault in response to the translation table walk identifying a fault condition for the target address, prefetch circuitry to generate a prefetch request to request prefetching of information associated with a prefetch target address to a cache; and faulting address prediction circuitry to predict whether the memory management circuitry would identify the fault condition for the prefetch target address if the translation table walk was performed by the memory management circuitry for the prefetch target address. In response to a prediction that the fault condition would be identified for the prefetch target address, the prefetch circuitry suppresses the prefetch request and the memory management circuitry prevents the translation table walk being performed for the prefetch target address of the prefetch request.

公开(公告)号：US20230120596A1

公开(公告)日：2023-04-20

申请号：US17505854

申请日：2021-10-20

Applicant: Arm Limited

Inventor： Joseph Michael PUSDESRIS ,  Nicholas Andrew PLANTE ,  Yasuo ISHII ,  Chris ABERNATHY

IPC: G06F9/38 ,  G06F9/30

Abstract: A predicated-loop-terminating branch instruction controls, based on whether a loop termination condition is satisfied, whether the processing circuitry should process a further iteration of a predicated loop body or process a following instruction. If at least one unnecessary iteration of the predicated loop body is processed following a mispredicted-non-termination branch misprediction when the loop termination condition is mispredicted as unsatisfied for a given iteration when it should have been satisfied, processing of the at least one unnecessary iteration of the predicated loop body is predicated to suppress an effect of the at least one unnecessary iteration. When the mispredicted-non-termination branch misprediction is detected for the given iteration of the predicated-loop-terminating branch instruction, in response to determining that a flush suppressing condition is satisfied, flushing of the at least one unnecessary iteration of the predicated loop body is suppressed as a response to the mispredicted-non-termination branch misprediction.