Abstract:
A circuit for a low-power and blocker-tolerant mixer-amplifier stage may include a complementary mixer formed by transmission gates having complementary structures. The complementary mixer may be configured to receive one or more radio-frequency (RF) signals and to convert the one or more RF signals to intermediate frequency (IF) current signals. A complementary TIA may be coupled to the complementary mixer and may be configured to receive the IF current signals and provide IF voltage signals. The complementary TIA may be formed by coupling an NMOS-TIA and a PMOS-TIA to a common load. A first portion of the complementary mixer may be coupled to the NMOS-TIA and a second portion of the complementary mixer may be coupled to the PMOS-TIA.
Abstract:
A method for reciprocal-mixing noise cancellation may include receiving a baseband signal down-converted to baseband using a local oscillator (LO). The baseband signal may comprise a wanted signal and a reciprocal mixing noise, which at least partially overlaps the wanted signal and is due to mixing of a blocker signal with a phase noise of the LO. Blocker recovery may be performed on the baseband signal and a blocker estimate signal may be generated from the baseband signal. The phase noise of the LO may be measured and used in generating a phase noise measurement signal. The blocker estimate signal and the phase noise measurement signal may be processed to generate a reconstructed noise signal that may comprise the overlapping reciprocal mixing noise. The reconstructed noise signal may be subtracted from the baseband signal to provide the wanted signal free from to the reciprocal mixing noise.
Abstract:
A circuit for a receiver with reconfigurable low-power or wideband operation may comprise one or more main signal paths each coupled to a first port and including a low-noise amplifier (LNA) configured to provide a radio frequency (RF) signal to a main mixer circuit. An auxiliary signal path may be coupled to a second port. The auxiliary signal path may include an auxiliary mixer configured to provide an on-chip matching input impedance that may match an impedance of the antenna. The first port may be coupled to an RF antenna through an off-chip matching circuit, when a low-power operation is desired. The first port may be coupled to the second port and to the RF antenna, when a wideband operation is desired.
Abstract:
A technique for calibration of on-chip resistance (R) and capacitance (C) values using an on-board bypass capacitor may include configuring an on-chip switch to selectively couple an on-chip calibration circuit to an on-chip port. The on-chip calibration circuit may include an RC oscillator having an RC time constant (RCTC). The on-board bypass capacitor may be coupled to the on-chip calibration circuit, by using the on-chip port. The on-chip R and C values may be calibrated using the on-chip calibration circuit and the on-board bypass capacitor.
Abstract:
A circuit for a low-noise interface between an amplifier and an analog-to-digital converter (ADC) may comprise a capacitor element having a capacitance of C coupled between a first and second output node of the amplifier. A first resistor R1 may be coupled in parallel with the capacitor. A second resistor R2 may be coupled between the first output node of the amplifier and a first input node of the ADC. A third resistor R3 may be coupled between the second output node of the amplifier and a second input node of the ADC. Initial values of the resistances R1, R2, and R3 may be selected to provide a desired value RL for a load resistance of the amplifier. A value of the capacitance C may be selected so that, in combination with the desired value RL, a desired bandwidth for the amplifier is achieved.
Abstract:
A circuit for a receiver with reconfigurable low-power or wideband operation may comprise one or more main signal paths each coupled to a first port and including a low-noise amplifier (LNA) configured to provide a radio frequency (RF) signal to a main mixer circuit. An auxiliary signal path may be coupled to a second port. The auxiliary signal path may include an auxiliary mixer configured to provide an on-chip matching input impedance that may match an impedance of the antenna. The first port may be coupled to an RF antenna through an off-chip matching circuit, when a low-power operation is desired. The first port may be coupled to the second port and to the RF antenna, when a wideband operation is desired.
Abstract:
A system for cancellation of a reciprocal-mixing noise may comprise a down-converter mixer that may be configured to down convert a radio-frequency (RF) signal and to generate a baseband signal. The RF signal may include a desired signal and a blocker signal. A first signal path may be configured to receive the baseband signal and to generate a first signal. A second signal path may be configured to receive the baseband signal and to generate a second signal. A subtraction module may be configured to subtract the second signal from the first signal and to generate an output signal. The second signal may comprise the reciprocal-mixing noise, and the output signal may comprise the desired signal substantially free from the reciprocal-mixing noise.
Abstract:
An RF front-end with on-chip transmitter/receiver isolation using a gyrator is presented herein. The RF front end is configured to support full-duplex communication and includes a gyrator and a transformer. The gyrator includes two transistors that are configured to isolate the input of a low-noise amplifier (LNA) from the output of a power amplifier (PA). The gyrator is further configured to isolate the output of the PA from the input of the LNA. The gyrator is at least partially or fully capable of being integrated on silicon-based substrate.
Abstract:
A power distributing duplexer system is provided. In some aspects, the system includes a duplexer configured to couple an antenna to a transmitter and a receiver. The system also includes a balancing network coupled to the duplexer. The balancing network includes a network impedance. The balancing network is configured to adjust the network impedance to match an antenna impedance of the antenna. The balancing network includes a plurality of balancing network modules coupled to the duplexer. Each of the plurality of balancing network modules is configured to receive a portion of an output voltage from the duplexer.