-
11.发明授权System for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tag 失效用于发出并行执行指令的系统，在分支到一组成员指令之后，具有口语标签中的复合性
公开(公告)号：US5303356A
公开(公告)日：1994-04-12
申请号：US677685
申请日：1991-03-29
CPC分类号： G06F9/3853 , G06F9/30152 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/382 , G06F9/3885
摘要： An instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in the instruction format text enabling the execution of the compound instruction format text in said instruction processor with a compounding facility which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units of the instruction processor while preserving intact the scalar execution of the base instructions of a scalar machine which were originally in storage. The system nullifies any execution of a member instruction unit of a compound instruction upon occurrence of possible conditions, such as branch, which would affect the correctness of recording results of execution of the member instruction unit portion based upon the interrelationship of member units of the compound instruction with other instructions. The resultant series of compounded instructions generally executes in a faster manner than the original format which is preserved due to the parallel nature of the compounded instruction stream which is executed.
摘要翻译： 一种指令处理器系统，用于对由标量机的一系列基本指令产生的复合指令进行解码，该处理器产生具有指令格式文本的指令格式文本的一系列复合指令，该指令格式文本具有能够执行复合指令格式的指令格式文本中的附加控制位 所述指令处理器中的文本具有复合设备，该复合设备提取和解码可由指令处理器的算术和逻辑单元作为复合指令和单个指令执行的复合指令，同时完整地保持标量机的基本指令的标量执行， 最初在存储。 该系统在发生可能的条件（例如分支）时，使复合指令的成员指令单元的任何执行无效，这将基于化合物的成员单元的相互关系而影响成员指令单元部分执行的记录结果的正确性 指令与其他指令。 所得到的一系列复合指令通常比由被执行的复合指令流的并行特性而保留的原始格式更快地执行。
-
12.发明授权Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit 失效用于与在执行单元中执行的其他指令同步地去除并同时执行两个或更多个分支指令的流水线
公开(公告)号：US5287467A
公开(公告)日：1994-02-15
申请号：US687309
申请日：1991-04-18
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/383 , G06F9/3832 , G06F9/3844 , G06F9/3885
摘要： The parallelism of a multi-pipelined digital computer is enhanced by detection of branch instructions from the execution pipelines and concurrent processing of up to two of the detected instructions in parallel with the operations of the execution pipelines. Certain branch instructions, when detected, are removed altogether from the pipeline, but still processed. The processing is synchronized with the execution pipeline to, first, predict an outcome for detected branch instructions, second, test the conditions for branch instructions at their proper place in the execution sequence to determine whether the predicted outcome was correct, and third, fetch a corrected target instruction if the prediction proves wrong.
摘要翻译： 多行数字计算机的并行性通过检测来自执行流水线的分支指令和最多两个检测到的指令与执行管线的操作并行处理来增强。 当检测到某些分支指令完全从管道中删除，但仍然被处理。 该处理与执行流水线同步，首先预测检测到的分支指令的结果，其次，在执行序列中的适当位置测试分支指令的条件，以确定预测结果是否正确，第三，获取 如果预测错误，则修正目标指令。
-
13.发明授权Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism 失效数字计算机系统能够并行处理两个或多个指令，并具有一个COCHE和指令的组合机制
公开(公告)号：US5214763A
公开(公告)日：1993-05-25
申请号：US522291
申请日：1990-05-10
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3853
摘要： A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
-
14.发明授权System for obtaining parallel execution of existing instructions in a particulr data processing configuration by compounding rules based on instruction categories 失效用于通过基于指令类别的规则复合来获得特定数据处理配置中的现有指令并行执行的系统
公开(公告)号：US5732234A
公开(公告)日：1998-03-24
申请号：US699689
申请日：1996-08-15
CPC分类号： G06F9/382 , G06F9/3017 , G06F9/3808 , G06F9/3842 , G06F9/3853 , G06F9/3885
摘要： A system for processing a sequence of instructions has a set of compounding rules based on an analysis of existing instructions to separate them into different classes. The analysis determines which instructions qualify, either with instructions in their own class or with instructions in other classes, for parallel execution in a particular hardware configuration. Such compounding rules are used as a standard for pre-processing an instruction stream in order to look for groups of two or more adjacent scalar instructions that can be executed in parallel.
摘要翻译： 用于处理指令序列的系统具有基于对现有指令的分析的一组复合规则，以将它们分成不同的类。 该分析决定哪些指令符合其自己的类别中的指令或其他类中的指令，用于在特定硬件配置中并行执行。 这种复合规则被用作预处理指令流的标准，以便寻找可以并行执行的两个或更多个相邻标量指令的组。
-
15.发明授权Memory management for scalable compound instruction set machines with in-memory compounding 失效具有内存组合的可扩展化合物指令集机器的内存管理
公开(公告)号：US5197135A
公开(公告)日：1993-03-23
申请号：US543458
申请日：1990-06-26
CPC分类号： G06F9/3808 , G06F9/30152 , G06F9/3802 , G06F9/3853
摘要： A digital computer system is described which is capable of processing 2 or more computer instructions in parallel and which has the capability of generating compounding tag information for those instructions, the compounding tag information being associated with instructions for the purpose of indicating groups of instructions which are to be concurrently executed. A compounding tag has a value which indicates the size of the group of instructions which are to be concurrently executed. The computer system includes a hierarchially-arranged memory which provides instructions to a CPU for execution. The instructions are compounded in the memory, and provision is made in the memory for storage of their compounding tags. In the event of modification of an instruction in memory, the invention provides for reduction of the value of the compounding tags for the modified instruction and instructions which are capable of being compounded with the modified instruction or for generation of new tag values for the modified instruction and instructions which are adjacent it in memory.
-
公开(公告)号：US5590348A
公开(公告)日：1996-12-31
申请号：US920962
申请日：1992-07-28
CPC分类号： G06F7/764 , G06F9/30032 , G06F9/30094 , G06F9/30167 , G06F9/3885
摘要： Generation of functional status followed by the use of the status to control the sequencing of microinstructions is a well known critical path in processor designs. The delay associated with the path is exacerbated in superscalar machines by the additional statuses that are produced by multiple functional units from which the appropriate status must be selected for controlling the sequencing of microinstructions. This is especially true in horizontally microcoded machines. The adverse affects on the delay can be reduced by using a staged multiplexor design. For the staged multiplexor to be useful, all functional unit status should be produced as early as possible. In this invention, a status predictor is described that allows the status associated with the shifter to be generated directly from the inputs to the shifter. As a result, the status is available early in the pipeline cycle in which the shift is actually performed and made available to the multiplexor producing the controls for microinstruction sequencing. In addition, the invention allows the early generation of all shifter status used to set condition codes. The predictor has been implemented in an ESA/390 processor implementation where it was instrumental in achieving the desired cycle time.
摘要翻译： 功能状态的产生，随后使用状态来控制微指令的排序是处理器设计中众所周知的关键路径。 与超标量机相关的延迟通过由多个功能单元产生的附加状态而加剧，由此必须选择适当的状态来控制微指令的排序。 在水平微编机器中尤其如此。 可以通过使用分段多路复用器设计来减少对延迟的不利影响。 为了使分级多路复用器有用，所有功能单元的状态应尽可能早地生成。 在本发明中，描述了状态预测器，其允许直接从移位器的输入产生与移位器相关联的状态。 因此，该状态在流水线周期的早期可用，其中实际执行移位并使其可用于产生用于微指令排序的控制的多路复用器。 此外，本发明允许早期生成用于设置条件代码的所有移位器状态。 预测器已经在ESA / 390处理器实现中实现，它在实现期望的周期时间方面发挥了重要作用。
-
17.发明授权System and method for obtaining parallel existing instructions in a particular data processing configuration by compounding instructions 失效用于通过复合指令在特定数据处理配置中获得并行存在的指令的系统和方法
公开(公告)号：US5502826A
公开(公告)日：1996-03-26
申请号：US186221
申请日：1994-01-25
CPC分类号： G06F9/382 , G06F9/3017 , G06F9/3808 , G06F9/3842 , G06F9/3853 , G06F9/3885
摘要： Scalable compound instruction set machine and method which provides for processing a set of instructions or program to be executed by a computer to determine statically which instructions may be combined into compound instructions which are executed in parallel by a scalar machine. Such processing looks for classes of instructions that can be executed in parallel without data-dependent or hardware-dependent interlocks. Without regard to their original sequence the individual instructions are combined with one or more other individual instructions to form a compound instruction which eliminates interlocks. Control information is appended to identify information relevant to the execution of the compound instructions. The result is a stream of scalar instructions compounded or grouped together before instruction decode time so that they are already flagged and identified for selective simultaneous parallel execution by execution units. The compounding does not change the object code results and existing programs realize performance improvements while maintaining compatibility with previously implemented systems for which the original set of instructions was provided.
摘要翻译： 可扩展复合指令集机器和方法，其提供用于处理由计算机执行的一组指令或程序，以静态地确定哪些指令可以组合成由标量机器并行执行的复合指令。 这样的处理查找可以并行执行的指令类，而不依赖于数据或依赖于硬件的互锁。 不考虑它们的原始顺序，单独的指令与一个或多个其他单独指令组合以形成消除互锁的复合指令。 附加控制信息以识别与复合指令的执行相关的信息。 结果是在指令解码时间之前复合或分组在一起的标量指令流，使得它们已经被标记和标识，以便由执行单元进行选择性同时并行执行。 复合不改变目标代码结果，现有程序实现性能改进，同时保持与提供原始指令集的先前实现的系统的兼容性。
-
18.发明授权Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel 失效用于缓存的复合预处理器用于识别可以并行执行的多个指令
公开(公告)号：US5465377A
公开(公告)日：1995-11-07
申请号：US126457
申请日：1993-09-24
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3017 , G06F9/3808 , G06F9/3812 , G06F9/3842 , G06F9/3853 , G06F9/3885
摘要： A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and generating for to each instruction a compounding information which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit with the compounding information. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the compounding information for the instructions is examined and those instructions indicated for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
摘要翻译： 一种数字计算机系统，其能够并行处理两个或更多个计算机指令，并且具有高速缓存存储单元，用于在从计算机系统的更高级存储单元到处理指令的功能单元之间临时存储机器级计算机指令 。 该计算机系统包括位于上级存储单元中间的指令复合单元和高速缓存存储单元，用于分析指令，并为每个指令生成指示该指令是否可以与一个或者另一个并行处理的复合信息 更多相邻指令在指令流中。 然后将这些标记的指令与复合信息一起存储在高速缓存单元中。 计算机系统还包括彼此并行操作的多个功能指令处理单元。 提供给这些功能单元的指令从缓存存储单元获得。 在指令发布时，检查指令的复合信息，并根据其操作码字段的编码将指示用于并行处理的指令发送到不同的功能单元。
-
19.发明授权Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel 失效用于缓存的复合预处理器用于识别可以并行执行的多个指令
公开(公告)号：US5295249A
公开(公告)日：1994-03-15
申请号：US642011
申请日：1991-01-15
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3017 , G06F9/3808 , G06F9/3812 , G06F9/3842 , G06F9/3853 , G06F9/3885
摘要： A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and generating for to each instruction a compounding information which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit with the compounding information. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the compounding information for the instructions is examined and those instructions indicated for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
摘要翻译： 一种数字计算机系统，其能够并行处理两个或更多个计算机指令，并且具有高速缓存存储单元，用于在从计算机系统的更高级存储单元到处理指令的功能单元之间临时存储机器级计算机指令 。 该计算机系统包括位于上级存储单元中间的指令复合单元和高速缓存存储单元，用于分析指令，并为每个指令生成指示该指令是否可以与一个或者另一个并行处理的复合信息 更多相邻指令在指令流中。 然后将这些标记的指令与复合信息一起存储在高速缓存单元中。 计算机系统还包括彼此并行操作的多个功能指令处理单元。 提供给这些功能单元的指令从缓存存储单元获得。 在指令发布时，检查指令的复合信息，并根据其操作码字段的编码将指示用于并行处理的指令发送到不同的功能单元。
-
20.发明授权Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines 有权用于将作业调度到多个硬件加速引擎的动态配置的硬件队列公开(公告)号：US09448846B2
公开(公告)日：2016-09-20
申请号：US13323914
申请日：2011-12-13
申请人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, Jr. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
发明人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, Jr. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
CPC分类号： G06F9/5038 , G06F9/4843 , G06F9/5027 , G06F2209/5021
摘要： A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.
摘要翻译： 一种具有多个处理资源的计算机系统，包括用于向多个硬件加速器调度和调度处理作业的子系统，所述子系统还包括作业请求器，用于请求具有有限和变化的延迟的作业以在硬件上执行 加速器 队列控制器，用于管理针对多个硬件加速器的处理作业请求; 以及用于将作业分派到所述多个硬件加速引擎的多个硬件队列，每个队列具有专用的队列入口头部，动态共享具有可配置队列深度限制的队列条目池，以及用于移除所有队列中的一个或多个作业的装置 。
-
-
-
-
-
-
-
-
-
搜索结果
49 条记录 (耗时 0.023 秒)
