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    Shallow trench isolation formation with no polish stop
    11.
    发明授权
    Shallow trench isolation formation with no polish stop 失效
    浅沟隔离形成，无抛光停止

    公开(公告)号：US6090712A

    公开(公告)日：2000-07-18

    申请号：US992489

    申请日：1997-12-18

    申请人： Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Obok

    发明人： Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Obok

    IPC分类号： H01L21/762 ,  H01L21/461

    CPC分类号： H01L21/76224

    摘要： An insulated trench isolation structure is formed in a semiconductor substrate omitting a barrier nitride polish stop layer while avoiding substrate damage, thereby simplifying trench formation and improving planarity. After trench fill, polishing is conducted to effect substantial planarization without exposing the substrate surface, thereby avoiding substrate damage. Etching is then conducted to expose the substrate surface. The omission of the barrier nitride polish stop avoids generation of a topographical step at the substrate/trench fill interface, thereby enhancing the accuracy of subsequent photolithographic techniques in forming features with minimal dimensions.

    摘要翻译： 在半导体衬底中形成绝缘沟槽隔离结构，省略了阻挡氮化物抛光停止层，同时避免了衬底损坏，从而简化了沟槽形成并提高了平面度。 在沟槽填充之后，进行抛光以实现基本平坦化而不暴露衬底表面，从而避免衬底损坏。 然后进行蚀刻以暴露衬底表面。 阻挡氮化物抛光停止的省略避免了在衬底/沟槽填充界面处产生形貌步骤，从而在最小尺寸形成特征的同时提高随后的光刻技术的精度。

    Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization
    12.
    发明授权
    Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization 失效
    用于制造具有最佳多晶硅互连布局的集成电路的掩模生成技术，用于实现全局平坦化

    公开(公告)号：US5894168A

    公开(公告)日：1999-04-13

    申请号：US947521

    申请日：1997-10-02

    申请人： Mark W. Michael ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  William S. Brennan

    发明人： Mark W. Michael ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  William S. Brennan

    IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L23/528 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/76819 ,  H01L21/31053 ,  H01L23/528 ,  H01L2924/0002

    摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

    摘要翻译： 提供了一种光刻掩模衍生方法，用于改善沉积在由衍生的光刻掩模形成的导体上的层间电介质的整体平面性。 衍生出光刻掩模，使得非操作导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，其上可使用例如化学机械的电介质层沉积并容易地平坦化 抛光技术。 所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。 操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。 非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。 因此，非操作导体对集成电路功能没有贡献，而不是为覆盖的层间电介质提供结构平面性。 掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。

    Method of formation of an air gap within a semiconductor dielectric by solvent desorption
    14.
    发明授权
    Method of formation of an air gap within a semiconductor dielectric by solvent desorption 失效
    通过溶剂解吸形成半导体电介质内气隙的方法

    公开(公告)号：US5759913A

    公开(公告)日：1998-06-02

    申请号：US658547

    申请日：1996-06-05

    申请人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

    发明人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

    IPC分类号： H01L21/768 ,  H01L21/283

    CPC分类号： H01L21/7682 ,  H01L21/76828

    摘要： A dielectric material is provided having air gaps which form during dielectric deposition between interconnects. The dielectric is deposited in interconnect-spaced geometries which have certain aspect ratios and which are exposed at the bottom of the geometries to a hygroscopic dielectric. During deposition, the dielectric is forced along the sidewall of the spaced interconnects as a result of moisture ougasing from the hygroscopic dielectric. Over a period of time, a keyhole occurs with pile up accumulation (or cusping) at the corners of the spaced interconnects. By decreasing the deposition temperature in a subsequent step, outgasing is minimized, and deposition over the keyhole and upon the hygroscopic dielectric takes place. Keyhole coverage results in an air gap which is surrounded on all sides by the fill dielectric. Air gap between interconnects helps reduce permittivity of the overall dielectric structure, resulting in a lessening of the interconnect line-to-line capacitance.

    摘要翻译： 提供介电材料，其具有在互连之间的介电沉积期间形成的气隙。 电介质沉积在具有特定纵横比的互连隔开的几何形状中，并且在几何形状的底部暴露于吸湿电介质。 在沉积期间，电介质由于从吸湿介质的湿气渗出而沿着间隔开的互连件的侧壁被迫。 在一段时间内，在间隔互连的角落处堆积积聚（或缩小）时，会产生锁孔。 通过在随后的步骤中降低沉积温度，最大限度地减少了沉积，并且在钥匙孔和吸湿介质上沉积。 钥匙孔覆盖导致气隙由填充电介质所包围。 互连之间的空气间隙有助于降低整个电介质结构的介电常数，导致互连线对线电容的减小。

    Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
    16.
    发明授权
    Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization 有权
    由沟槽限定并被氧化物覆盖以改善平坦化的半导体隔离区

    公开(公告)号：US06353253B2

    公开(公告)日：2002-03-05

    申请号：US09227914

    申请日：1999-01-08

    申请人： Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark W. Michael ,  William S. Brennan

    发明人： Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark W. Michael ,  William S. Brennan

    IPC分类号： H01L2900

    CPC分类号： H01L21/76205 ,  H01L21/76229

    摘要： An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.

    摘要翻译： 提供隔离技术用于改善隔离区域相对于相邻有源区硅台面的整体平面度。 隔离过程导致在紧邻有源区域的场区域中形成沟槽。 然而，这个沟槽并不完全穿过田野区域。 通过防止大面积沟槽，避免了大量的介电填充材料以及该填充材料随后的平坦化问题。 因此，本发明的隔离技术不需要通常与浅沟槽工艺相关联的常规填充电介质。 虽然它实现了形成硅台面的优点，但是本方法避免了使用常规的牺牲回蚀，块掩模和化学机械抛光在大面积场区域中的电介质表面的返修。 其改进的隔离技术利用在场区周边蚀刻到硅衬底中的最小宽度的沟槽，留下场台面。 在场台面上形成场电介质，优选氧化物，并填充场台面和有源台面之间的沟槽，留下与相邻活性台面的上表面相当的基本上平面的场电介质。

    Shallow trench isolation formation with spacer-assisted ion implantation
    17.
    发明授权
    Shallow trench isolation formation with spacer-assisted ion implantation 有权
    浅沟槽隔离形成与间隔子辅助离子注入

    公开(公告)号：US6143624A

    公开(公告)日：2000-11-07

    申请号：US172088

    申请日：1998-10-14

    申请人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

    发明人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76235 ,  H01L21/76237 ,  Y10S438/966 ,  Y10S438/981

    摘要： An insulated trench isolation structure is formed by ion implanting impurities proximate the trench edges to enhance the silicon oxidation rate and, hence, increase the thickness of the resulting oxide at the trench edges. Embodiments include masking and etching a barrier nitride layer, forming protective spacers on portions of the substrate corresponding to subsequently formed trench edges, etching the trench, removing the protective spacers, ion implanting impurities into those portions of the substrate previously covered by the protective spacers, and then growing an oxide liner. The resulting oxide formed on the trench edges is thick due to the enhanced silicon oxidation rate, thereby avoiding overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.

    摘要翻译： 通过离子注入靠近沟槽边缘的杂质形成绝缘沟槽隔离结构，以增强硅的氧化速率，并因此增加在沟槽边缘处产生的氧化物的厚度。 实施例包括掩蔽和蚀刻阻挡氮化物层，在对应于随后形成的沟槽边缘的衬底的部分上形成保护性间隔物，蚀刻沟槽，去除保护性间隔物，将先前被保护隔离层覆盖的衬底的离子注入杂质， 然后生长氧化物衬垫。 形成在沟槽边缘上的所得氧化物由于硅氧化速率的增强而变厚，从而避免随后沉积的多晶硅层的重叠以及伴随沟槽边缘处的薄化栅极氧化物的破坏问题。

    Stepper alignment mark structure for maintaining alignment integrity
    19.
    发明授权
    Stepper alignment mark structure for maintaining alignment integrity 有权
    用于保持对准完整性的步进对准标记结构

    公开(公告)号：US6037671A

    公开(公告)日：2000-03-14

    申请号：US184861

    申请日：1998-11-03

    申请人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

    发明人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

    IPC分类号： G03F9/00 ,  H01L23/544

    CPC分类号： G03F9/7076 ,  G03F9/70 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

    摘要： Accurate photolighographic processing is achieved employing a stepper global alignment structure enabling formation thereon of a substantially transparent layer having a substantially planar upper surface. Embodiments include a set of global alignment marks comprising spaced apart trenches, each trench segmented into a plurality of narrow trenches spaced apart by uprights and forming a dummy topographical area of narrow trenches surrounding the set of alignment marks. The segmented trenches and the dummy topographical area effectively provide a substantially uniform topography enabling deposition of a transparent layer without steps and effective local planarization. Since the upper surface of the transparent layer is substantially planar, layers of material deposited on the transparent layer during subsequent processing also have a substantially planar upper surface, thereby enabling transmission of the signal produced by the alignment marks to the stepper with minimal distortion.

    摘要翻译： 使用步进全局对准结构可实现准确的视差处理，该结构能够在其上形成具有基本平坦的上表面的基本上透明的层。 实施例包括一组包括间隔开的沟槽的全局对准标记，每个沟槽被分段成由立柱间隔开的多个窄沟槽，并形成围绕该组对准标记的窄沟槽的虚拟地形区域。 分段沟槽和虚拟地形区域有效地提供基本均匀的形貌，使得能够沉积透明层而无需步骤和有效的局部平面化。 由于透明层的上表面基本上是平面的，因此在随后的处理期间沉积在透明层上的材料层也具有基本平坦的上表面，从而能够以最小的变形将由对准标记产生的信号传输到步进机。