公开(公告)号：US06316293B1

公开(公告)日：2001-11-13

申请号：US09531749

申请日：2000-03-20

申请人： Hao Fang

发明人： Hao Fang

IPC分类号： H01L21335

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546

摘要： A method of forming a NAND-type flash memory device including forming a stacked gate flash memory structure (346) containing an interpoly dielectric layer (322) for one or more flash memory cells in a core region (305). The method also includes forming a select gate transistor structure (348) having a first gate oxide (322) formed of the interpoly dielectric material and a gate conductor (338) overlying the first gate oxide (322) in the core region (305). A NAND-type flash memory device includes a core region (305) comprising a stacked gate flash memory cell structure (346) and a select gate transistor (348) and a periphery region (314, 315) comprising a low voltage transistor (342) and a high voltage transistor (350). The stacked gate flash memory cell structure (346) includes a tunnel oxide layer (308), a poly1 layer (312) overlying the tunnel oxide layer (308), an interpoly dielectric layer (322) formed of an insulating material overlying the poly1 layer (312) and a poly2 layer (338) overlying the interpoly dielectric layer (322). In addition, the select gate transistor structure (348) includes a gate insulator (322) formed of the insulating material and a poly2 layer (338) overlying the gate insulator (322).

摘要翻译： 一种形成NAND型闪速存储器件的方法，包括形成堆叠的栅极闪存结构（346），该堆叠栅极闪存结构（346）包含用于核心区域（305）中的一个或多个闪速存储器单元的互聚电介质层（322）。 该方法还包括形成选择栅极晶体管结构（348），该选择栅极晶体管结构（348）具有由多晶硅间介电材料形成的第一栅极氧化物（322）和覆盖芯区域（305）中的第一栅极氧化物（322）的栅极导体（338）。 NAND型闪速存储器件包括包括堆叠栅极快闪存储器单元结构（346）和选择栅极晶体管（348）的核心区域（305）和包括低压晶体管（342）的外围区域（314,315） 和高压晶体管（350）。 层叠栅极快闪存储单元结构（346）包括隧道氧化物层（308），覆盖隧道氧化物层（308）的多晶硅层（312），由绝缘材料形成的多晶硅绝缘层（322） （312）和覆盖在多晶硅间介电层（322）上的多晶硅层（338）。 此外，选择栅极晶体管结构（348）包括由绝缘材料形成的栅极绝缘体（322）和覆盖栅极绝缘体（322）的多晶硅层（338）。

公开(公告)号：US06312991B1

公开(公告)日：2001-11-06

申请号：US09531582

申请日：2000-03-21

申请人： John Jianshi Wang ,  Hao Fang ,  Masaaki Higashitani

发明人： John Jianshi Wang ,  Hao Fang ,  Masaaki Higashitani

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： A method (200) of forming a NAND type flash memory device includes the steps of forming an oxide layer (202) over a substrate (102) and forming a first conductive layer (106) over the oxide layer. The first conductive layer (106) is etched to form a gate structure (107) in a select gate transistor region (105) and a floating gate structure (106a, 106b) in a memory cell region (111). A first insulating layer (110) is then formed over the memory cell region (111) and a second conductive layer (112, 118) is formed over the first insulating layer (110). A word line (122) is patterned in the memory cell region (111) to form a control gate region and source and drain regions (130, 132) are formed in the in the substrate (102) in a region adjacent the word line (122) and in a region adjacent the gate structure (107). A second insulating layer (140) is formed over both the select gate transistor region (105) and the memory cell region (111) and first and second contact openings are formed in the second insulating layer (140) down to the gate structure (107) and the control gate region, wherein a depth (X) through the second insulating layer (140) down to the gate structure (107) and down to the control gate region are approximately the same, thereby eliminating a substantial overetch of the gate structure contact opening.

摘要翻译： 形成NAND型快闪存储器件的方法（200）包括以下步骤：在衬底（102）上形成氧化物层（202），并在氧化物层上形成第一导电层（106）。 蚀刻第一导电层（106）以在存储单元区域（111）中的选择栅极晶体管区域（105）和浮动栅极结构（106a，106b）中形成栅极结构（107）。 然后在存储单元区域（111）之上形成第一绝缘层（110），并且在第一绝缘层（110）之上形成第二导电层（112,118）。 在存储单元区域（111）中对字线（122）进行构图以形成控制栅极区域，并且在邻近字线的区域（102,132）中形成在衬底（102）中的源极和漏极区域（130,132） 122）并且在与栅极结构（107）相邻的区域中。 在选择栅极晶体管区域（105）和存储单元区域（111）上形成第二绝缘层（140），并且在第二绝缘层（140）中形成第一和第二接触开口至栅极结构（107） ）和控制栅极区域，其中通过第二绝缘层（140）到达栅极结构（107）并且向下到控制栅极区域的深度（X）大致相同，从而消除了栅极结构的实质上的过蚀刻 接触开口

公开(公告)号：US06211058B1

公开(公告)日：2001-04-03

申请号：US09353781

申请日：1999-07-15

申请人： John Jianshi Wang ,  Hao Fang

发明人： John Jianshi Wang ,  Hao Fang

IPC分类号： H01L214763

CPC分类号： H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S438/911 ,  H01L2924/00

摘要： A semiconductor device having multiple layers uses different size contacts at different layer in order in order to simply the manufacturing process and the depth of etching required. Contact sizes are selected based on the responsiveness of the material to the etching process. Where a deep etch is required, a larger contact is used. A shallower etch through similar material uses a smaller contact to slow the etching process. As a result, the etches can complete at about the same time. The technique can be employed to etch any number of contacts. An intermediate size contact can be used where the material to be etched results in a slower etching process. A plurality of contact sizes can be used depending on the depths of etching required and the characteristics material to be etched, so that the etching for all the contacts completes at substantially the same time.

摘要翻译： 具有多层的半导体器件按顺序在不同的层上使用不同尺寸的触点，以便简单地制造工艺和所需的蚀刻深度。 触点尺寸是根据材料对蚀刻工艺的响应性来选择的。 在需要深刻蚀时，使用较大的接触。 通过类似材料的较浅蚀刻使用更小的接触来减缓蚀刻工艺。 因此，蚀刻可以在大约相同的时间完成。 该技术可用于蚀刻任何数量的触点。 可以使用中等尺寸的接触件，其中待蚀刻的材料导致较慢的蚀刻工艺。 可以根据所需的蚀刻深度和要蚀刻的特征材料使用多个接触尺寸，使得所有触点的蚀刻基本上同时完成。

公开(公告)号：US06188606B1

公开(公告)日：2001-02-13

申请号：US09369600

申请日：1999-08-06

申请人： Narbeh Derhacobian ,  Hao Fang ,  Michael Han

发明人： Narbeh Derhacobian ,  Hao Fang ,  Michael Han

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5642

摘要： A method and circuit for sensing multi states of a NAND memory cell by varying source bias, at a constant gate voltage, preferably zero volts, generating a memory cell current in response to the source bias, and sensing the memory cell state.

摘要翻译： 一种用于通过在恒定栅极电压（优选为零伏特）下改变源偏置来感测NAND存储器单元的多状态的方法和电路，响应于源极偏置产生存储单元电流，并感测存储单元状态。

公开(公告)号：US6143612A

公开(公告)日：2000-11-07

申请号：US172090

申请日：1998-10-14

申请人： Narbeh Derhacobian ,  Pau-ling Chen ,  Hao Fang ,  Timothy Thurgate

发明人： Narbeh Derhacobian ,  Pau-ling Chen ,  Hao Fang ,  Timothy Thurgate

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/76216 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/78

摘要： A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is forced while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, and employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants. Appropriate openings are formed in the field implant blocking mask so that the field implant occurs at the edges of the junctions, thus achieving low leakage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

摘要翻译： 强制显示高门控二极管击穿电压，低泄漏和低体效应的高电压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括通过掩蔽来自常规场注入的高电压结点来提供高门控二极管击穿电压，从传统的阈值调整注入屏蔽源极/漏极区域，以及采用非常轻掺杂的n型注入来代替常规的n +和 LDD植入物。 在场注入阻挡掩模中形成适当的开口，使得场注入发生在接合部的边缘处，从而实现低泄漏。 场注入阻挡掩模在沟道区域上延伸，从而产生具有低体效应的晶体管。

公开(公告)号：US08572756B2

公开(公告)日：2013-10-29

申请号：US13078051

申请日：2011-04-01

申请人： Hui Hu ,  Hao Fang ,  Qingyan Liu

发明人： Hui Hu ,  Hao Fang ,  Qingyan Liu

IPC分类号： G06F7/02

CPC分类号： G06F21/36 ,  G06Q30/0241 ,  H04L63/083

摘要： A CAPTCHA method executed by a CAPTCHA system is provided, comprising: receiving a CAPTCHA request comprising category information of an application service from an application server; responding to the application server with a token identifying the CAPTCHA request and a CAPTCHA image comprising a distorted advertisement word associated to the category information and a series of randomly generated and distorted characters, both the advertisement word and the characters being a CAPTCHA text intended to be typed by a user via a user equipment connected to the application server; receiving from the application server the token and a CAPTCHA answer submitted from the user equipment by the user; and verifying the token and the answer and returning to the application server a result of the verification. This provides an improved CAPTCHA system and method with better advertising effects and security.

摘要翻译： 提供了一种由CAPTCHA系统执行的CAPTCHA方法，包括：从应用服务器接收包括应用服务的类别信息的CAPTCHA请求; 用标识CAPTCHA请求的令牌对应用服务器进行响应;以及CAPTCHA图像，其包括与类别信息相关联的失真广告词和一系列随机生成和失真的字符，所述广告词和所述字符都是想要成为的CAPTCHA文本 由用户通过连接到应用服务器的用户设备键入; 从应用服务器接收令牌和由用户从用户设备提交的CAPTCHA答案; 并验证令牌和答案，并向应用服务器返回验证结果。 这提供了一种改进的CAPTCHA系统和方法，具有更好的广告效果和安全性。

公开(公告)号：US08507969B2

公开(公告)日：2013-08-13

申请号：US13465649

申请日：2012-05-07

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

摘要翻译： 公开了一种用于在闪速存储器件中提供至少一个触点的方法和系统。 闪速存储器件包括多个栅极堆叠，并且至少包括一个包括多晶硅层作为顶表面的部件。 该方法和系统还包括在多晶硅层的顶表面上形成硅化物，并提供覆盖多个栅叠层，至少一个元件和硅化物的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供至少一个接触孔。 绝缘层蚀刻步骤使用硅化物作为蚀刻停止层，以确保绝缘蚀刻步骤​​不会蚀刻穿过多晶硅层。 该方法和系统还包括用导体填充至少一个接触孔。

公开(公告)号：US07466508B2

公开(公告)日：2008-12-16

申请号：US10776701

申请日：2004-02-11

申请人： Hao Fang ,  Cameron C. Rabe

发明人： Hao Fang ,  Cameron C. Rabe

IPC分类号： G11B5/02

CPC分类号： G11B5/012 ,  G11B2005/0013

摘要： An impedance matched write circuit is provided that shunts one or more matching resistors. The impedance matched write circuit includes an interconnect for connecting to a write head and at least one resistor between a control voltage and the interconnect for impedance matching to the interconnect. A transistor can be connected across the resistor to shunt current that would otherwise pass through the resistor during an overshoot mode. The transistor may be a PMOS transistor or a combination of PMOS and NMOS transistors. A gate voltage of the transistor is controlled by a source such that the transistor is turned on in an overshoot mode and turned off during a steady state mode.

摘要翻译： 提供阻抗匹配写电路，其分流一个或多个匹配电阻器。 阻抗匹配写入电路包括用于连接到写入头的互连和用于与互连的阻抗匹配的控制电压和互连之间的至少一个电阻器。 晶体管可以跨过电阻连接，以分流电流，否则在过冲模式下电流将通过电阻。 晶体管可以是PMOS晶体管或PMOS和NMOS晶体管的组合。 晶体管的栅极电压由源极控制，使得晶体管以过冲模式导通，并在稳态模式期间截止。

公开(公告)号：US20070147119A1

公开(公告)日：2007-06-28

申请号：US11319908

申请日：2005-12-27

申请人： Tuan Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Hemink

发明人： Tuan Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Hemink

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534

摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.

摘要翻译： NAND闪存器件采用独特的增压板设计。 升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。 升压板还屏蔽浮动栅极之间的不必要的耦合。 自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。 因此，根据本发明可以实现更紧凑和可靠的存储器件。

公开(公告)号：US20060066973A1

公开(公告)日：2006-03-30

申请号：US10954599

申请日：2004-09-30

申请人： Hao Fang ,  Stephen Kuehne

发明人： Hao Fang ,  Stephen Kuehne

IPC分类号： G11B5/02 ,  G11B5/09

CPC分类号： H01F13/006 ,  G11B5/465

摘要： A demagnetizer for an inductive load having a driver circuit including at least one transistor and a ramp-down voltage source switchably connected to the driver circuit, so that when the ramp-down voltage source is connected to the transistor, it drives the voltage of the transistor below its threshold voltage.