公开(公告)号：US08183619B1

公开(公告)日：2012-05-22

申请号：US09539458

申请日：2000-03-30

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

公开(公告)号：US08329530B1

公开(公告)日：2012-12-11

申请号：US13566741

申请日：2012-08-03

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

摘要翻译： 公开了一种用于在闪速存储器件中提供至少一个触点的方法和系统。 闪速存储器件包括多个栅极堆叠，并且至少包括一个包括多晶硅层作为顶表面的部件。 该方法和系统还包括在多晶硅层的顶表面上形成硅化物，并提供覆盖多个栅叠层，至少一个元件和硅化物的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供至少一个接触孔。 绝缘层蚀刻步骤使用硅化物作为蚀刻停止层，以确保绝缘蚀刻步骤​​不会蚀刻通过多晶硅层。 该方法和系统还包括用导体填充至少一个接触孔。

公开(公告)号：US06472327B2

公开(公告)日：2002-10-29

申请号：US09925205

申请日：2001-08-08

申请人： King Wai Kelwin Ko ,  Mark S. Chang ,  Hao Fang

发明人： King Wai Kelwin Ko ,  Mark S. Chang ,  Hao Fang

IPC分类号： H01L21304

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/11534

摘要： A method and system for etching gate oxide during transistor fabrication is disclosed. The method and system begin by depositing a gate oxide on a substrate, followed by a deposition of a tunnel oxide mask over a portion of the gate oxide. The method and system further include performing a combination dry/wet-etch to remove the gate oxide uncovered by the tunnel oxide mask, which minimizes tunnel oxide undercut.

摘要翻译： 公开了在晶体管制造期间蚀刻栅极氧化物的方法和系统。 该方法和系统首先通过在衬底上沉积栅极氧化物，然后在栅极氧化物的一部分上沉积隧道氧化物掩模。 该方法和系统还包括执行干/湿蚀刻组合以去除未被隧道氧化物掩模覆盖的栅极氧化物，其使隧道氧化物底切最小化。

公开(公告)号：US06445051B1

公开(公告)日：2002-09-03

申请号：US09563797

申请日：2000-05-02

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko ,  John Jianshi Wang ,  Michael K. Templeton ,  Lu You ,  Angela T. Hui

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko ,  John Jianshi Wang ,  Michael K. Templeton ,  Lu You ,  Angela T. Hui

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L21/28273

摘要： A method and system for providing a plurality of contacts in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and a plurality of field insulating regions adjacent to a portion of the plurality of gate stacks. The method and system include providing an etch stop layer covering the plurality of field insulating regions. The etch stop layer has an etch selectivity different from a field insulating region etch selectivity of the plurality of field insulating regions. The method and system also include providing an insulating layer covering the plurality of gate stacks, the plurality of field insulating regions and the etch stop layer. The method and system further include etching the insulating layer to provide a plurality of contact holes. The insulating layer etching step uses the etch stop layer to ensure that the insulating etching step does not etch through the plurality of field insulating regions. The method and system also include filling the plurality of contact holes with a conductor.

摘要翻译： 公开了一种用于在闪速存储器件中提供多个触点的方法和系统。 闪存器件包括多个栅极堆叠和与多个栅极堆叠的一部分相邻的多个场绝缘区域。 该方法和系统包括提供覆盖多个场绝缘区域的蚀刻停止层。 蚀刻停止层具有与多个场绝缘区域的场绝缘区蚀刻选择性不同的蚀刻选择性。 该方法和系统还包括提供覆盖多个栅极叠层，多个场绝缘区域和蚀刻停止层的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供多个接触孔。 绝缘层蚀刻步骤使用蚀刻停止层来确保绝缘蚀刻步骤​​不会蚀刻穿过多个场绝缘区域。 该方法和系统还包括用导体填充多个接触孔。

公开(公告)号：US20120302017A1

公开(公告)日：2012-11-29

申请号：US13566741

申请日：2012-08-03

申请人： Mark S. CHANG ,  Hao Fang ,  King Wai Kelwin Ko

发明人： Mark S. CHANG ,  Hao Fang ,  King Wai Kelwin Ko

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

摘要翻译： 公开了一种用于在闪速存储器件中提供至少一个触点的方法和系统。 闪速存储器件包括多个栅极堆叠，并且至少包括一个包括多晶硅层作为顶表面的部件。 该方法和系统还包括在多晶硅层的顶表面上形成硅化物，并提供覆盖多个栅叠层，至少一个元件和硅化物的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供至少一个接触孔。 绝缘层蚀刻步骤使用硅化物作为蚀刻停止层，以确保绝缘蚀刻步骤​​不会蚀刻穿过多晶硅层。 该方法和系统还包括用导体填充至少一个接触孔。

公开(公告)号：US08507969B2

公开(公告)日：2013-08-13

申请号：US13465649

申请日：2012-05-07

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

摘要翻译： 公开了一种用于在闪速存储器件中提供至少一个触点的方法和系统。 闪速存储器件包括多个栅极堆叠，并且至少包括一个包括多晶硅层作为顶表面的部件。 该方法和系统还包括在多晶硅层的顶表面上形成硅化物，并提供覆盖多个栅叠层，至少一个元件和硅化物的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供至少一个接触孔。 绝缘层蚀刻步骤使用硅化物作为蚀刻停止层，以确保绝缘蚀刻步骤​​不会蚀刻穿过多晶硅层。 该方法和系统还包括用导体填充至少一个接触孔。

公开(公告)号：US06448594B1

公开(公告)日：2002-09-10

申请号：US09539307

申请日：2000-03-30

申请人： Maria C. Chan ,  Hao Fang ,  Lu You ,  Mark S. Chang ,  King Wai Kelwin Ko

发明人： Maria C. Chan ,  Hao Fang ,  Lu You ,  Mark S. Chang ,  King Wai Kelwin Ko

IPC分类号： H01L2976

CPC分类号： H01L21/823468 ,  H01L21/823425 ,  Y10S257/90

摘要： In a first aspect of the present invention, a semiconductor device is disclosed. The semiconductor device comprises at least two gate stacks, each gate stack having two sides and oxide spacers on each of the two sides of each of the at least two gate stacks, wherein at least one of the oxide spacers is triangular shaped. In a second aspect of the present invention, a method and system for processing a semiconductor device is disclosed. The method and system for processing a semiconductor comprise forming at least two gate stacks over a semiconductor substrate, depositing an oxide layer over the at least two gate stacks, and etching the oxide layer to form at least one oxide spacer in between the at least two gate stacks, wherein the at least one oxide spacer is triangular shape. Through the use the present invention, the voids that are created in the semiconductor device during conventional semiconductor processing are eliminated. This is accomplished by creating oxide spacers having a triangular shape when etching the oxide layer to form the oxide spacer. By creating a triangular shaped oxide spacer, subsequent layers of material can be deposited over the oxide spacer without creating voids in the semiconductor device. Accordingly, as a result of the use of the present invention, the oxide spacers are strengthened, which increases the reliability of the semiconductor device.

摘要翻译： 在本发明的第一方面中，公开了一种半导体器件。 半导体器件包括至少两个栅极堆叠，每个栅极堆叠体具有在所述至少两个栅极堆叠中的每一个的两侧上的两个侧面和氧化物间隔物，其中至少一个氧化物间隔物是三角形的。 在本发明的第二方面中，公开了一种用于处理半导体器件的方法和系统。 用于处理半导体的方法和系统包括在半导体衬底上形成至少两个栅极叠层，在所述至少两个栅极堆叠上沉积氧化物层，以及蚀刻氧化物层以在至少两个栅极堆叠之间形成至少一个氧化物间隔物 栅堆叠，其中所述至少一个氧化物间隔物是三角形的。 通过使用本发明，消除了在常规半导体处理期间在半导体器件中产生的空隙。 这通过在蚀刻氧化物层以形成氧化物间隔物时形成具有三角形形状的氧化物间隔物来实现。 通过产生三角形氧化物间隔物，随后的材料层可沉积在氧化物间隔物上，而不会在半导体器件中产生空隙。 因此，作为使用本发明的结果，氧化物间隔物被加强，这增加了半导体器件的可靠性。

公开(公告)号：US06603211B2

公开(公告)日：2003-08-05

申请号：US09784907

申请日：2001-02-15

申请人： Michael K. Templeton ,  Hao Fang ,  Maria C. Chan ,  King Wai Kelwin Ko

发明人： Michael K. Templeton ,  Hao Fang ,  Maria C. Chan ,  King Wai Kelwin Ko

IPC分类号： H01L23544

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and system for providing an alignment mark for a thin layer in a semiconductor device is disclosed. The semiconductor device includes at least one alternative part having a first thickness greater than a second thickness of the thin layer. The method and system include providing the thin layer and providing the alignment mark for the thin layer in the at least one alternative part. The alignment mark has a depth that is greater than the second thickness of the thin layer. In one aspect, the method and system include providing a mask for the thin layer. The mask includes an alignment mark portion that covers the at least one alternative part and that is for providing the alignment mark. In this aspect, the method and system also include removing a portion of the at least one alternative part to provide the alignment mark in the at least one alternative part.

公开(公告)号：US06251776B1

公开(公告)日：2001-06-26

申请号：US09283754

申请日：1999-04-02

申请人： Minh Van Ngo ,  Simon S. Chan ,  Anne E. Sanderfer ,  King Wai Kelwin Ko

发明人： Minh Van Ngo ,  Simon S. Chan ,  Anne E. Sanderfer ,  King Wai Kelwin Ko

IPC分类号： H01L21441

CPC分类号： H01L21/02071 ,  H01L21/02052 ,  H01L21/02054 ,  H01L21/76838

摘要： Stress corrosion induced voiding of patterned metal layers is avoided or substantially reduced by removing etching residues before gap filling. Embodiments include etching an Al or Al alloy layer employing fluorine and/or chlorine chemistry, wet cleaning, treating with a plasma containing ammonia or ammonia and oxygen at a temperature of at least about 400° C. and gap filling with a dielectric material, e.g. HDP oxide by HDP CVD.

摘要翻译： 通过在间隙填充之前去除蚀刻残留物来避免或显着减少图形化金属层的应力腐蚀引起的空隙。 实施例包括使用氟和/或氯化学，湿洗，用至少约400℃的温度下含有氨或氨和等离子体的等离子体进行蚀刻Al或Al合金层，以及填充介电材料的间隙。 HDP CVD的HDP氧化物。

公开(公告)号：US06333263B1

公开(公告)日：2001-12-25

申请号：US09285388

申请日：1999-04-02

申请人： Minh Van Ngo ,  Simon S. Chan ,  Anne E. Sanderfer ,  King Wai Kelwin Ko

发明人： Minh Van Ngo ,  Simon S. Chan ,  Anne E. Sanderfer ,  King Wai Kelwin Ko

IPC分类号： H01L2144

CPC分类号： H01L21/76838

摘要： Stress corrosion induced voiding of patterned metal layers is avoided or substantially reduced by removing etching residues before gap filling. Embodiments include etching an Al or Al alloy layer employing fluorine and/or chlorine chemistry, wet cleaning, treating with a nitrogen-containing plasma at a temperature of at least about 400° C. and gap filling with a dielectric material, e.g. HDP oxide by HDPCVD.

摘要翻译： 通过在间隙填充之前去除蚀刻残留物来避免或显着减少图形化金属层的应力腐蚀引起的空隙。 实施方案包括使用氟和/或氯化学，湿法清洗，在至少约400℃的温度下用含氮等离子体进行蚀刻和用电介质材料填充间隙来蚀刻Al或Al合金层。 HDPVD的HDP氧化物。