公开(公告)号：US08183619B1

公开(公告)日：2012-05-22

申请号：US09539458

申请日：2000-03-30

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

公开(公告)号：US08329530B1

公开(公告)日：2012-12-11

申请号：US13566741

申请日：2012-08-03

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

摘要翻译： 公开了一种用于在闪速存储器件中提供至少一个触点的方法和系统。 闪速存储器件包括多个栅极堆叠，并且至少包括一个包括多晶硅层作为顶表面的部件。 该方法和系统还包括在多晶硅层的顶表面上形成硅化物，并提供覆盖多个栅叠层，至少一个元件和硅化物的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供至少一个接触孔。 绝缘层蚀刻步骤使用硅化物作为蚀刻停止层，以确保绝缘蚀刻步骤​​不会蚀刻通过多晶硅层。 该方法和系统还包括用导体填充至少一个接触孔。

公开(公告)号：US06472327B2

公开(公告)日：2002-10-29

申请号：US09925205

申请日：2001-08-08

申请人： King Wai Kelwin Ko ,  Mark S. Chang ,  Hao Fang

发明人： King Wai Kelwin Ko ,  Mark S. Chang ,  Hao Fang

IPC分类号： H01L21304

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/11534

摘要： A method and system for etching gate oxide during transistor fabrication is disclosed. The method and system begin by depositing a gate oxide on a substrate, followed by a deposition of a tunnel oxide mask over a portion of the gate oxide. The method and system further include performing a combination dry/wet-etch to remove the gate oxide uncovered by the tunnel oxide mask, which minimizes tunnel oxide undercut.

摘要翻译： 公开了在晶体管制造期间蚀刻栅极氧化物的方法和系统。 该方法和系统首先通过在衬底上沉积栅极氧化物，然后在栅极氧化物的一部分上沉积隧道氧化物掩模。 该方法和系统还包括执行干/湿蚀刻组合以去除未被隧道氧化物掩模覆盖的栅极氧化物，其使隧道氧化物底切最小化。

公开(公告)号：US06445051B1

公开(公告)日：2002-09-03

申请号：US09563797

申请日：2000-05-02

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko ,  John Jianshi Wang ,  Michael K. Templeton ,  Lu You ,  Angela T. Hui

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko ,  John Jianshi Wang ,  Michael K. Templeton ,  Lu You ,  Angela T. Hui

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L21/28273

摘要： A method and system for providing a plurality of contacts in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and a plurality of field insulating regions adjacent to a portion of the plurality of gate stacks. The method and system include providing an etch stop layer covering the plurality of field insulating regions. The etch stop layer has an etch selectivity different from a field insulating region etch selectivity of the plurality of field insulating regions. The method and system also include providing an insulating layer covering the plurality of gate stacks, the plurality of field insulating regions and the etch stop layer. The method and system further include etching the insulating layer to provide a plurality of contact holes. The insulating layer etching step uses the etch stop layer to ensure that the insulating etching step does not etch through the plurality of field insulating regions. The method and system also include filling the plurality of contact holes with a conductor.

摘要翻译： 公开了一种用于在闪速存储器件中提供多个触点的方法和系统。 闪存器件包括多个栅极堆叠和与多个栅极堆叠的一部分相邻的多个场绝缘区域。 该方法和系统包括提供覆盖多个场绝缘区域的蚀刻停止层。 蚀刻停止层具有与多个场绝缘区域的场绝缘区蚀刻选择性不同的蚀刻选择性。 该方法和系统还包括提供覆盖多个栅极叠层，多个场绝缘区域和蚀刻停止层的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供多个接触孔。 绝缘层蚀刻步骤使用蚀刻停止层来确保绝缘蚀刻步骤​​不会蚀刻穿过多个场绝缘区域。 该方法和系统还包括用导体填充多个接触孔。

公开(公告)号：US08507969B2

公开(公告)日：2013-08-13

申请号：US13465649

申请日：2012-05-07

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

摘要翻译： 公开了一种用于在闪速存储器件中提供至少一个触点的方法和系统。 闪速存储器件包括多个栅极堆叠，并且至少包括一个包括多晶硅层作为顶表面的部件。 该方法和系统还包括在多晶硅层的顶表面上形成硅化物，并提供覆盖多个栅叠层，至少一个元件和硅化物的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供至少一个接触孔。 绝缘层蚀刻步骤使用硅化物作为蚀刻停止层，以确保绝缘蚀刻步骤​​不会蚀刻穿过多晶硅层。 该方法和系统还包括用导体填充至少一个接触孔。

公开(公告)号：US06448594B1

公开(公告)日：2002-09-10

申请号：US09539307

申请日：2000-03-30

申请人： Maria C. Chan ,  Hao Fang ,  Lu You ,  Mark S. Chang ,  King Wai Kelwin Ko

发明人： Maria C. Chan ,  Hao Fang ,  Lu You ,  Mark S. Chang ,  King Wai Kelwin Ko

IPC分类号： H01L2976

CPC分类号： H01L21/823468 ,  H01L21/823425 ,  Y10S257/90

摘要： In a first aspect of the present invention, a semiconductor device is disclosed. The semiconductor device comprises at least two gate stacks, each gate stack having two sides and oxide spacers on each of the two sides of each of the at least two gate stacks, wherein at least one of the oxide spacers is triangular shaped. In a second aspect of the present invention, a method and system for processing a semiconductor device is disclosed. The method and system for processing a semiconductor comprise forming at least two gate stacks over a semiconductor substrate, depositing an oxide layer over the at least two gate stacks, and etching the oxide layer to form at least one oxide spacer in between the at least two gate stacks, wherein the at least one oxide spacer is triangular shape. Through the use the present invention, the voids that are created in the semiconductor device during conventional semiconductor processing are eliminated. This is accomplished by creating oxide spacers having a triangular shape when etching the oxide layer to form the oxide spacer. By creating a triangular shaped oxide spacer, subsequent layers of material can be deposited over the oxide spacer without creating voids in the semiconductor device. Accordingly, as a result of the use of the present invention, the oxide spacers are strengthened, which increases the reliability of the semiconductor device.

摘要翻译： 在本发明的第一方面中，公开了一种半导体器件。 半导体器件包括至少两个栅极堆叠，每个栅极堆叠体具有在所述至少两个栅极堆叠中的每一个的两侧上的两个侧面和氧化物间隔物，其中至少一个氧化物间隔物是三角形的。 在本发明的第二方面中，公开了一种用于处理半导体器件的方法和系统。 用于处理半导体的方法和系统包括在半导体衬底上形成至少两个栅极叠层，在所述至少两个栅极堆叠上沉积氧化物层，以及蚀刻氧化物层以在至少两个栅极堆叠之间形成至少一个氧化物间隔物 栅堆叠，其中所述至少一个氧化物间隔物是三角形的。 通过使用本发明，消除了在常规半导体处理期间在半导体器件中产生的空隙。 这通过在蚀刻氧化物层以形成氧化物间隔物时形成具有三角形形状的氧化物间隔物来实现。 通过产生三角形氧化物间隔物，随后的材料层可沉积在氧化物间隔物上，而不会在半导体器件中产生空隙。 因此，作为使用本发明的结果，氧化物间隔物被加强，这增加了半导体器件的可靠性。

公开(公告)号：US06610580B1

公开(公告)日：2003-08-26

申请号：US09563179

申请日：2000-05-02

申请人： Maria C. Chan ,  Hao Fang ,  Mark S. Chang ,  Mike Templeton

发明人： Maria C. Chan ,  Hao Fang ,  Mark S. Chang ,  Mike Templeton

IPC分类号： H01L2176

CPC分类号： H01L27/11521 ,  H01L21/76205 ,  H01L21/76224 ,  H01L27/11517

摘要： In a first aspect of the present invention, a flash memory array is disclosed. The flash memory array comprises a substrate comprising active regions, wherein the active regions are defined by a layer of nitride, the layer of nitride including a top surface. The flash memory array further comprises shallow trenches in the substrate, each of the shallow trenches including a layer of oxide, the layer of oxide having a top surface, wherein the top surface of the layer of oxide and the top surface of the layer of nitride are on substantially the same plane and channel areas wherein the occurrences of polyl stringers in the channel areas is substantially reduced. In a second aspect of the present invention, a method and system for fabricating a flash memory array is disclosed. The method comprises the steps of providing a layer of nitride over a substrate, forming trenches in the substrate and then growing a layer of oxide in the trenches. Finally, the layer of oxide is polished back. Through the use of the preferred embodiment of the present invention, a shallow trench isolation process is implemented as opposed to LOCOS process, thereby reducing the occurrence of polyl stringers in the channel area. Accordingly, the occurrence of unwanted electrical shorting paths between the adjacent regions is substantially reduced.

摘要翻译： 在本发明的第一方面，公开了一种闪存阵列。 闪存阵列包括包含有源区的衬底，其中有源区由氮化物层限定，氮化物层包括顶表面。 闪存阵列还包括衬底中的浅沟槽，每个浅沟槽包括一层氧化物，氧化层具有顶表面，其中氧化层的顶表面和氮化层的顶表面 在基本相同的平面和通道区域上，其中通道区域中多边形桁条的出现被大大减少。 在本发明的第二方面中，公开了一种用于制造闪存阵列的方法和系统。 该方法包括以下步骤：在衬底上提供氮化物层，在衬底中形成沟槽，然后在沟槽中生长一层氧化物。 最后，氧化层被抛光。 通过使用本发明的优选实施例，与LOCOS工艺相反，实现了浅沟槽隔离工艺，从而减少了通道区域中多边形的发生。 因此，相邻区域之间不需要的电短路径的发生显着减少。

公开(公告)号：US06979619B1

公开(公告)日：2005-12-27

申请号：US09941370

申请日：2001-08-28

申请人： Hao Fang ,  Yue-Song He ,  Mark S. Chang ,  Kent K. Chang

发明人： Hao Fang ,  Yue-Song He ,  Mark S. Chang ,  Kent K. Chang

IPC分类号： H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11543

摘要： In a first aspect of the present invention, a method of fabricating a flash memory device is disclosed. The method comprises the steps of providing a portion of a dual gate oxide in a periphery area of the memory device and then simultaneously providing a dual gate oxide in a core area of the memory device and completing the dual gate oxide in the periphery area. Finally, a nitridation process is provided in both the core and periphery areas subsequent to the previous steps. In a second aspect of the present invention, a flash memory device is disclosed. The flash memory device comprises core area having a plurality of memory transistors comprising an oxide layer, a first poly layer, an interpoly dielectric layer, and a second poly layer. The flash memory device further comprises a periphery area having a plurality of transistors comprising an oxide layer, a portion of the first poly layer, and the second poly layer. According to the present invention, the method for fabricating the flash memory device is a simplified process that results in a significant improvement in the oxide reliability in the core and periphery areas and also eliminates the nitrogen contamination problem in the periphery area.

摘要翻译： 在本发明的第一方面中，公开了一种制造闪速存储器件的方法。 该方法包括以下步骤：在存储器件的外围区域中提供双栅极氧化物的一部分，然后在存储器件的核心区域中同时提供双栅极氧化物，并在周边区域中完成双栅极氧化物。 最后，在上述步骤之后，在核心区域和外围区域都提供氮化处理。 在本发明的第二方面，公开了一种闪速存储器件。 闪存器件包括具有包括氧化物层，第一多晶硅层，多晶硅间介电层和第二多晶硅层的多个存储晶体管的核心区域。 闪存器件还包括具有包括氧化物层，第一多晶硅层的一部分和第二多晶硅层的多个晶体管的外围区域。 根据本发明，用于制造闪速存储器件的方法是简化的工艺，其显着提高了芯部和外围区域中的氧化物可靠性，并且还消除了周边区域中的氮污染问题。

公开(公告)号：US06815292B1

公开(公告)日：2004-11-09

申请号：US10260061

申请日：2002-09-27

申请人： Hao Fang ,  Mark S. Chang

发明人： Hao Fang ,  Mark S. Chang

IPC分类号： H01L2972

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531

摘要： A flash memory array having improved core field isolation in select gate regions via shallow trench isolation and field isolation implant after liner oxidation is disclosed. The flash memory array includes a core area and a periphery area, wherein the core area further includes a select gate region. The method of fabricating the flash memory array begins by patterning a layer of nitride over a substrate in active device locations. After the nitride is patterned, a silicon trench etch is performed to form trenches. After forming the trenches, a layer of liner oxide is grown in the trenches. Then, a field implant is performed in both the core area and periphery area to provide field isolation regions for the flash memory array with. Thereafter, poly1 is patterned in the core area to form floating gate and select word-lines.

公开(公告)号：US06638358B1

公开(公告)日：2003-10-28

申请号：US09483176

申请日：2000-01-13

申请人： Lu You ,  Mark S. Chang ,  Hao Fang

发明人： Lu You ,  Mark S. Chang ,  Hao Fang

IPC分类号： B05C500

CPC分类号： H01L21/02134 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/316 ,  H01L21/823468

摘要： The present invention is a method and system for processing a semiconductor device, the semiconductor device comprising at least two gate stacks and a spacer gap. The method and system comprise utilizing a spin-on technique at the transistor device level to provide an oxide spacer in the spacer gap and then curing the semiconductor device at a temperature above approximately 450° C. Through the use of a system/method in accordance with the present invention, the voids that are created in the spacer gaps during conventional semiconductor processing are eliminated. Furthermore, the oxide spacers posses the high quality characteristics that are typically provided through the use of the conventional CVD methodology. Accordingly, as a result of the use of the system/method in accordance with the present invention, the MOSFET oxide spacers are strengthened, which increases the reliability of the semiconductor device.

摘要翻译： 本发明是用于处理半导体器件的方法和系统，该半导体器件包括至少两个栅极叠层和间隔物间隙。 该方法和系统包括利用晶体管器件级上的旋涂技术在间隔物间隙中提供氧化物隔离物，然后在高于约450℃的温度下固化半导体器件。通过使用根据本发明的系统/方法 利用本发明，消除了在常规半导体处理期间在间隔物间隙中产生的空隙。 此外，氧化物间隔物具有通常通过使用常规CVD方法提供的高质量特性。 因此，通过使用根据本发明的系统/方法的结果，MOSFET氧化物间隔物被加强，这增加了半导体器件的可靠性。