公开(公告)号：US07538411B2

公开(公告)日：2009-05-26

申请号：US11411994

申请日：2006-04-26

申请人： Josef Willer ,  Klaus-Dieter Ufert

发明人： Josef Willer ,  Klaus-Dieter Ufert

IPC分类号： H01L29/00

CPC分类号： H01L45/14 ,  B82Y10/00 ,  G11C13/00 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/32 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675 ,  H01L45/1683

摘要： Wordline stacks are arranged parallel at a distance from one another on a substrate surface. Bitlines are arranged transversely to the wordline stacks at a distance from one another. Source/drain regions are formed as doped regions in the vicinity of the wordline stacks. A resistive layer is disposed between a plurality of the source/drain regions and the bitlines and formed of a material having a resistance that is switched by an applied voltage. Source lines are arranged parallel to the wordline stacks so that they connect further pluralities of the source/drain regions.

摘要翻译： 字线堆叠在衬底表面上彼此间隔一定距离平行排列。 位线横向于彼此间隔一定距离的字线堆栈布置。 源极/漏极区域形成为字线堆叠附近的掺杂区域。 电阻层设置在多个源极/漏极区域和位线之间，并且由具有通过施加电压切换的电阻的材料形成。 源极线平行于字线堆栈布置，使得它们连接更多个源极/漏极区域。

公开(公告)号：US20090097317A1

公开(公告)日：2009-04-16

申请号：US11872655

申请日：2007-10-15

申请人： Josef Willer ,  Franz Hofmann ,  Detlev Richter ,  Nicolas Nagel

发明人： Josef Willer ,  Franz Hofmann ,  Detlev Richter ,  Nicolas Nagel

IPC分类号： G11C16/00 ,  H01L21/336 ,  H01L29/788

CPC分类号： G11C16/0483 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/11568

摘要： Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.

摘要翻译： 本发明的实施例一般涉及用于制造集成电路的集成电路和方法。 在本发明的实施例中，提供了具有存储单元的集成电路。 存储单元可以包括载体中的沟槽，沟槽中的电荷俘获层结构，电荷俘获层结构包括至少两个分离的电荷俘获区，至少部分填充在沟槽中的导电材料以及源/漏区 旁边的沟槽。

公开(公告)号：US20090026524A1

公开(公告)日：2009-01-29

申请号：US11829700

申请日：2007-07-27

申请人： Franz Kreupl ,  Josef Willer ,  Doris Keitel-Schulz

发明人： Franz Kreupl ,  Josef Willer ,  Doris Keitel-Schulz

IPC分类号： H01L29/788 ,  H01L21/30 ,  H01L23/48

CPC分类号： H01L27/115 ,  H01L21/76254 ,  H01L21/8221 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/00

摘要： An integrated circuit includes a first integrated circuit layer including at least one first transistor channel region and having a wafer bonding interface. The integrated circuit may further include at least one second integrated circuit layer including at least one second transistor channel region and being arranged at the wafer bonding interface of the first integrated circuit layer.

摘要翻译： 集成电路包括包括至少一个第一晶体管沟道区并具有晶片接合界面的第一集成电路层。 集成电路还可以包括至少一个包括至少一个第二晶体管沟道区的第二集成电路层，并布置在第一集成电路层的晶片接合界面处。

公开(公告)号：US20080237694A1

公开(公告)日：2008-10-02

申请号：US11728960

申请日：2007-03-27

申请人： Michael Specht ,  Nicolas Nagel ,  Josef Willer

发明人： Michael Specht ,  Nicolas Nagel ,  Josef Willer

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L29/513

摘要： The invention relates to integrated circuits, to a cell, to a cell arrangement, to a method for manufacturing an integrated circuit, to a method for manufacturing a cell, and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a cell, the cell including a low-k dielectric layer, a first high-k dielectric layer disposed above the low-k dielectric layer, a charge trapping layer disposed above the first high-k dielectric layer, and a second high-k dielectric layer disposed above the charge trapping layer.

摘要翻译： 本发明涉及集成电路，单元，单元布置，集成电路的制造方法，单元的制造方法以及存储器模块。 在本发明的实施例中，提供了具有单元的集成电路，该单元包括低k电介质层，设置在低k电介质层上方的第一高k电介质层，设置在第一 高k电介质层和设置在电荷捕获层上方的第二高k电介质层。

公开(公告)号：US20080225587A1

公开(公告)日：2008-09-18

申请号：US11686211

申请日：2007-03-14

申请人： Nicolas Nagel ,  Josef Willer

发明人： Nicolas Nagel ,  Josef Willer

IPC分类号： G11C11/34

CPC分类号： H01L27/115 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578

摘要： The present invention relates generally to integrated circuits, to methods for manufacturing integrated circuits, and to integrated memory arrays.

摘要翻译： 本发明一般涉及集成电路，集成电路的制造方法以及集成存储器阵列。

公开(公告)号：US07341904B2

公开(公告)日：2008-03-11

申请号：US11367731

申请日：2006-03-03

申请人： Josef Willer

发明人： Josef Willer

IPC分类号： H01L21/8239

CPC分类号： H01L27/1203 ,  H01L27/108 ,  H01L27/10876 ,  H01L29/7841 ,  Y10S257/906

摘要： A semiconductor device is fabricated by forming a trench in a semiconductor body. A region of dielectric material is formed within at least a lower portion of the trench. An upper portion of the semiconductor body is doped. A cutout is formed in the semiconductor material such that a vertical strip of semiconductor material remains along a sidewall of the dielectric material. A lower portion of the semiconductor body adjacent the sidewall of the dielectric material is doped. A gate dielectric layer is formed over the vertical strip of semiconductor material and a gate electrode is arranged in the cutout.

摘要翻译： 通过在半导体本体中形成沟槽来制造半导体器件。 电介质材料的区域形成在沟槽的至少下部内。 掺杂半导体本体的上部。 在半导体材料中形成切口，使得半导体材料的垂直条沿着电介质材料的侧壁保留。 与电介质材料的侧壁相邻的半导体本体的下部被掺杂。 栅电介质层形成在半导体材料的垂直条上，栅电极设置在切口中。

公开(公告)号：US20070284650A1

公开(公告)日：2007-12-13

申请号：US11448134

申请日：2006-06-07

申请人： Josef Willer

发明人： Josef Willer

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A memory device includes active regions extending in a first direction, the active regions being formed in a semiconductor substrate. Transistors are formed in the active regions, including a first and a second source/drain region, a channel formed between the first and the second source/drain region, a gate electrode, and a charge storage layer stack disposed between the gate electrode and the channel, where adjacent active regions are isolated from each other by fin isolation grooves. Wordlines extend in a second direction, and each wordline is connected with a plurality of gate electrodes that are assigned to different active regions. The active regions are formed as ridges in the semiconductor substrate, with the word lines and the charge storing layer stack being disposed adjacent to at least two sides of each of the active regions. Each of the ridges has a top portion and a bottom portion, where the maximum width of the top portion is larger than the minimum width of the bottom portion.

摘要翻译： 存储器件包括沿第一方向延伸的有源区，有源区形成在半导体衬底中。 晶体管形成在有源区域中，包括第一和第二源极/漏极区域，形成在第一和第二源极/漏极区域之间的沟道，栅极电极和电荷存储层堆叠，其设置在栅极电极和第二源极/漏极区域之间 通道，其中相邻的有源区域通过散热片隔离槽相互隔离。 字线在第二方向上延伸，并且每条字线与分配给不同有效区域的多个栅电极连接。 有源区域在半导体衬底中形成为脊，其中字线和电荷存储层堆叠被布置为与每个有源区域的至少两侧相邻。 每个脊具有顶部和底部，其中顶部的最大宽度大于底部的最小宽度。

公开(公告)号：US07272040B2

公开(公告)日：2007-09-18

申请号：US11119376

申请日：2005-04-29

申请人： Thomas Mikolajick ,  Josef Willer ,  Corvin Liaw

发明人： Thomas Mikolajick ,  Josef Willer ,  Corvin Liaw

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568

摘要： An array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of electrons into the memory layers. The write operation is effected by hot hole injection. A write voltage is applied by a bitline to two NAND chains in series. The subsequent bitline on the side of the memory cell to be programmed is maintained on floating potential, whereas the bitline on the other side is set to an inhibit voltage, which is provided to inhibit a program disturb of an addressed memory cell which is not to be programmed. This virtual-ground NAND architecture of charge-trapping memory cells enables an increased storage density.

摘要翻译： 一个电荷捕获多位存储单元的阵列被布置在虚拟地NAND架构中。 存储器单元被Fowler-Nordheim擦除，将电子隧穿到存储器层中。 写入操作通过热空穴注入来实现。 写入电压通过位线施加到两个串联的NAND链。 要编程的存储器单元侧的后续位线保持浮置电位，而另一侧的位线被设置为禁止电压，该禁止电压被提供以阻止寻址的存储器单元的程序干扰 被编程。 电荷俘获存储器单元的虚拟NAND架构能够提高存储密度。

公开(公告)号：US07186607B2

公开(公告)日：2007-03-06

申请号：US11061314

申请日：2005-02-18

申请人： Harald Seidl ,  Josef Willer ,  Martin Gutsche

发明人： Harald Seidl ,  Josef Willer ,  Martin Gutsche

IPC分类号： H01L21/8238

CPC分类号： H01L21/28282 ,  H01L27/105 ,  H01L27/11568 ,  H01L29/4234

摘要： A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of polysilicon. The SiGe layer can be etched selectively to the gate electrode and the gate oxide and is laterally removed adjacent the source/drain regions in order to form recesses, which are subsequently filled with a material that is appropriate for charge-trapping. The device structure and production method are appropriate for an integration scheme comprising local interconnects of memory cells, a CMOS logic periphery and means to compensate differences of the layer levels in the array and the periphery.

摘要翻译： 提供薄SiGe层作为附加的下栅电极层，并且布置在薄栅极氧化物和栅电极层之间，优选多晶硅。 SiGe层可以选择性地蚀刻到栅电极和栅极氧化物，并且在源极/漏极区附近被横向去除以形成凹槽，随后填充适合于电荷捕获的材料。 器件结构和制造方法适用于包括存储器单元的本地互连，CMOS逻辑外围和补偿阵列和外围中的层级差异的装置的集成方案。

公开(公告)号：US07184317B2

公开(公告)日：2007-02-27

申请号：US11172421

申请日：2005-06-30

申请人： Thomas Roehr ,  Josef Willer

发明人： Thomas Roehr ,  Josef Willer

IPC分类号： G11C11/34

CPC分类号： G11C16/12

摘要： A programming voltage is applied to source and drain in order to generate hot-hole injection at one end of the channel of a memory cell. The undesired programming of a neighboring memory cell is avoided by the application of an intermediate inhibit voltage to an adjacent bitline. This is done by precharging all the bitlines to the inhibit voltage, either by successively applying the inhibit voltage to every bitline individually or by applying both the upper and the lower programming voltage to one half of the bitlines and then short-circuiting all the bitlines to produce an intermediate voltage.

摘要翻译： 将编程电压施加到源极和漏极，以便在存储器单元的沟道的一端产生热空穴注入。 通过向相邻位线施加中间禁止电压来避免相邻存储器单元的不期望​​的编程。 这可以通过将所有位线预充电到抑制电压来完成，方法是通过将禁止电压单独地连续施加到每个位线，或者通过将上限和下限编程电压同时施加到位线的一半，然后将所有位线短路到 产生中间电压。