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48 条记录 (耗时 0.013 秒)

    MEMORY CIRCUIT
    1.
    发明申请
    MEMORY CIRCUIT 审中-公开
    存储器电路

    公开(公告)号：US20080056041A1

    公开(公告)日：2008-03-06

    申请号：US11469746

    申请日：2006-09-01

    申请人： Corvin Liaw ,  Michael Markert ,  Stefan Dietrich ,  Milena Dimitrova

    发明人： Corvin Liaw ,  Michael Markert ,  Stefan Dietrich ,  Milena Dimitrova

    IPC分类号： G11C7/02

    CPC分类号： G11C7/18 ,  G11C7/02 ,  G11C7/06 ,  G11C2207/005

    摘要： A memory circuit comprises a plurality of parallel bit-lines connected to a plurality of memory cells, a plurality of sense amplifiers connected to the bit-lines and a plurality of switches each of which being connected to a respective pair of bit-lines out of the plurality of bit-lines for switchably short-circuiting the respective pair of bit-lines. The bit-lines of the respective pair of bit-lines are connected to two different sense amplifiers, and the bit-lines of the respective pair of bit-lines are adjacent to a further bit-line disposed between the bit-lines of the respective pair of bit-lines.

    摘要翻译： 存储电路包括连接到多个存储器单元的多个并行位线，连接到位线的多个读出放大器和多个开关，每个开关连接到相应的一对位线， 所述多个位线用于可切换地使相应的一对位线短路。 相应的位线对的位线连接到两个不同的读出放大器，并且相应的位线对的位线与设置在相应的位线之间的位线之间的另一个位线相邻 一对位线。

    Memory circuit and method for reading out a memory datum from such a memory circuit
    2.
    发明授权
    Memory circuit and method for reading out a memory datum from such a memory circuit 有权
    用于从这样的存储器电路读出存储器数据的存储器电路和方法

    公开(公告)号：US07254052B2

    公开(公告)日：2007-08-07

    申请号：US11287501

    申请日：2005-11-25

    申请人： Corvin Liaw

    发明人： Corvin Liaw

    IPC分类号： G11C7/00

    CPC分类号： G11C7/14 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/79

    摘要： The present invention relates to a memory circuit comprising a CBRAM resistance memory cell, which is connected to a bit line and a word line and has a CBRAM resistance element, the resistance of which can be set by means of a write current, in order to store an item of information, and which has a selection switch, which can be driven via the word line, in order to connect a first potential to the bit line via the CBRAM resistance element; a reference resistance cell, which is connected to the bit line and to a reference line and has a reference resistance element, the resistance of which is set to a resistance threshold value, and a reference selection switch, which can be driven via the reference line, in order to connect a second potential to the bit line via the reference resistance element; a read-out unit, which is configured to activate the reference selection switch and the selection switch for the purpose of reading out a memory datum, so that a memory cell current flows via the CBRAM resistance memory cell and a reference current flows via the reference resistance cell onto the bit line; and an evaluation unit, which is connected to the bit line, and which outputs the memory datum in a manner dependent on a resulting electrical quantity assigned to the bit line.

    摘要翻译： 本发明涉及一种存储器电路，其包括CBRAM电阻存储单元，其连接到位线和字线并且具有CBRAM电阻元件，其电阻可以通过写入电流来设置，以便 存储一条信息，并且具有可以经由字线驱动的选择开关，以便经由CBRAM电阻元件将第一电位连接到位线; 参考电阻单元，其连接到位线和参考线，并且具有电阻被设置为电阻阈值的参考电阻元件和可以经由参考线驱动的参考选择开关 以便通过参考电阻元件将第二电位连接到位线; 读出单元，其被配置为激活参考选择开关和选择开关以便读出存储器数据，使得存储单元电流经由CBRAM电阻存储单元流动，并且参考电流通过参考流动 电阻单元到位线上; 以及评估单元，其连接到位线，并且以取决于分配给位线的所得电量的方式输出存储器基准。

    Resistive memory arrangement
    4.
    发明授权
    Resistive memory arrangement 有权
    电阻记忆布置

    公开(公告)号：US07215568B2

    公开(公告)日：2007-05-08

    申请号：US11215443

    申请日：2005-08-30

    申请人： Corvin Liaw ,  Thomas Roehr ,  Michael Kund

    发明人： Corvin Liaw ,  Thomas Roehr ,  Michael Kund

    IPC分类号： G11C11/00

    CPC分类号： G11C13/003 ,  G11C13/0011 ,  G11C2213/78 ,  G11C2213/79

    摘要： Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.

    摘要翻译： 提供了具有以行和列构成的单元阵列并且具有连接到用于驱动的​​驱动元件的电阻性存储单元的电阻式存储器装置。 每个驱动元件共同连接到形成存储单元的n个单元电阻器，单元电阻器是CBRAM电阻元件，特别是与CBRAM电阻元件实现的用于电阻存储器布置的写入，读取和擦除方法。

    Method for operating a PMC memory cell and CBRAM memory circuit
    5.
    发明申请
    Method for operating a PMC memory cell and CBRAM memory circuit 有权
    操作PMC存储单元和CBRAM存储器电路的方法

    公开(公告)号：US20060265548A1

    公开(公告)日：2006-11-23

    申请号：US11133716

    申请日：2005-05-20

    申请人： Ralf Symanczyk ,  Corvin Liaw

    发明人： Ralf Symanczyk ,  Corvin Liaw

    IPC分类号： G06F13/28

    CPC分类号： G11C13/0069 ,  G11C13/0011 ,  G11C13/0033 ,  G11C16/3431 ,  G11C2013/009 ,  G11C2213/79

    摘要： The present invention relates to a method for operating a PMC memory cell for use in a CBRAM memory array, wherein the PMC memory cell includes a solid electrolyte which is adapted to selectively develop and diminish a conductive path depending on an applied electrical field. The PMC memory cell is programmed to change to a programmed state by applying a programming voltage, and the PMC memory cell is erased to change to an erased state by applying an erase voltage. A refresh voltage is applied to the PMC memory cell at a predetermined time to stabilize the programmed state of the PMC memory cell, wherein the refresh voltage is selected such as that, while applying the refresh voltage, a programming of the PMC memory cell in the erased state to a programmed state is prevented, and that, by applying the refresh voltage, a stabilizing of the programmed state of the PMC memory cell is performed.

    摘要翻译： 本发明涉及一种用于操作用于CBRAM存储器阵列的PMC存储单元的方法，其中PMC存储单元包括固体电解质，其适于根据所施加的电场选择性地显影和减少导电路径。 通过应用编程电压将PMC存储单元编程为改变为编程状态，并通过施加擦除电压擦除PMC存储单元以改变为擦除状态。 在预定时间对PMC存储单元施加刷新电压以稳定PMC存储单元的编程状态，其中选择刷新电压，例如，在施加刷新电压时，在PMC存储单元的编程中 防止擦除状态到编程状态，并且通过施加刷新电压，执行PMC存储单元的编程状态的稳定。

    Method of Operating an Integrated Circuit, Integrated Circuit, and Memory Module
    9.
    发明申请
    Method of Operating an Integrated Circuit, Integrated Circuit, and Memory Module 有权
    操作集成电路，集成电路和存储器模块的方法

    公开(公告)号：US20090021976A1

    公开(公告)日：2009-01-22

    申请号：US11778549

    申请日：2007-07-16

    申请人： Corvin Liaw ,  Michael Angerbauer ,  Peter Schroegmeier

    发明人： Corvin Liaw ,  Michael Angerbauer ,  Peter Schroegmeier

    IPC分类号： G11C11/00

    CPC分类号： G11C13/00 ,  G11C5/02 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/79

    摘要： A method of operating an integrated circuit is provided. The integrated circuit includes a plurality of resistivity changing memory cells and at least one resistivity changing reference cell; a voltage comparator including a first input terminal and a second input terminal; a signal line being connected to the plurality of resistivity changing memory cells, the at least one resistivity changing reference cell, and the second input terminal; and a switching element connecting the first input terminal to the second input terminal. The method includes: closing the switching element; supplying a first voltage to the first input terminal via the signal line and the switching element; opening the switching element; supplying a second voltage to the second input terminal via the signal line; and comparing the first voltage and the second voltage using the voltage comparator, wherein the first voltage represents a memory state of a resistivity changing memory cell, and the second voltage is a reference voltage which represents a memory state of a resistivity changing reference cell, or vice versa.

    摘要翻译： 提供一种操作集成电路的方法。 集成电路包括多个电阻率变化存储单元和至少一个电阻率变化参考单元; 电压比较器，包括第一输入端子和第二输入端子; 信号线连接到所述多个电阻率变化存储单元，所述至少一个电阻率变化参考单元和所述第二输入端子; 以及将第一输入端子连接到第二输入端子的开关元件。 该方法包括：闭合开关元件; 经由所述信号线和所述开关元件向所述第一输入端提供第一电压; 打开开关元件; 经由信号线向第二输入端提供第二电压; 以及使用所述电压比较器来比较所述第一电压和所述第二电压，其中所述第一电压表示电阻率变化存储单元的存储状态，所述第二电压是表示电阻率变化参考单元的存储状态的参考电压，或 反之亦然。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07440303B2

    公开(公告)日：2008-10-21

    申请号：US11724057

    申请日：2007-03-14

    申请人： Corvin Liaw

    发明人： Corvin Liaw

    IPC分类号： G11C27/00

    CPC分类号： G11C13/0011 ,  G11C2213/79

    摘要： A semiconductor memory device includes resistance memory elements that are coupled to selection transistors addressed by word lines and bit lines. The memory elements are read by read/write lines arranged parallel to the word lines. Two successive memory elements along a read/write line are coupled to selection transistors that are coupled to different word lines.

    摘要翻译： 半导体存储器件包括耦合到由字线和位线寻址的选择晶体管的电阻存储器元件。 存储器元件由与字线平行布置的读/写线读取。 沿着读/写线的两个连续存储元件耦合到耦合到不同字线的选择晶体管。