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公开(公告)号：US20090026524A1
公开(公告)日：2009-01-29
申请号：US11829700
申请日：2007-07-27
申请人： Franz Kreupl , Josef Willer , Doris Keitel-Schulz
发明人： Franz Kreupl , Josef Willer , Doris Keitel-Schulz
IPC分类号： H01L29/788 , H01L21/30 , H01L23/48
CPC分类号： H01L27/115 , H01L21/76254 , H01L21/8221 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L27/11 , H01L27/1104 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L2224/83894 , H01L2225/06513 , H01L2225/06541 , H01L2924/13091 , H01L2924/00
摘要： An integrated circuit includes a first integrated circuit layer including at least one first transistor channel region and having a wafer bonding interface. The integrated circuit may further include at least one second integrated circuit layer including at least one second transistor channel region and being arranged at the wafer bonding interface of the first integrated circuit layer.
摘要翻译： 集成电路包括包括至少一个第一晶体管沟道区并具有晶片接合界面的第一集成电路层。 集成电路还可以包括至少一个包括至少一个第二晶体管沟道区的第二集成电路层，并布置在第一集成电路层的晶片接合界面处。
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2.发明申请Integrated Circuit with an Active Area Line Having at Least One Form-Supporting Element and Corresponding Method of Making an Integrated Circuit 有权具有至少一个支撑元件的有源面积线的集成电路和制造集成电路的相应方法公开(公告)号：US20100019345A1
公开(公告)日：2010-01-28
申请号：US12177930
申请日：2008-07-23
IPC分类号： H01L21/3065 , H01L23/58
CPC分类号： H01L21/28273 , H01L21/3086 , H01L21/32139 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.
摘要翻译： 描述了集成电路。 集成电路可以具有：由具有与半导体衬底的上表面平行的第一纵向方向的半导体衬底的材料形成的有源区线; 其中所述有源面积线具有至少一个形状支撑元件，所述支撑元件在平行于所述半导体衬底的上表面的第二纵向方向上延伸; 并且其中所述第二纵向方向相对于所述第一纵向方向以不等于0度并且不等于180度的角度布置。
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3.发明申请公开(公告)号：US20090261397A1
公开(公告)日：2009-10-22
申请号：US12104750
申请日：2008-04-17
申请人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
发明人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11521
摘要： An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.
摘要翻译： 描述了集成电路。 集成电路可以包括多个浮栅电极，其中浮栅电极中的至少一个具有较低宽度和上宽度，下宽度大于上宽度，并且其中至少一个 浮栅电极包括过渡金属。 还描述了集成电路的相应制造方法。
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4.发明授权Integrated circuit with an active area line having at least one form-supporting element and corresponding method of making an integrated circuit 有权具有至少一个形式支撑元件的有源面积线的集成电路和制造集成电路的对应方法公开(公告)号：US07868415B2
公开(公告)日：2011-01-11
申请号：US12177930
申请日：2008-07-23
IPC分类号： H01L23/58
CPC分类号： H01L21/28273 , H01L21/3086 , H01L21/32139 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.
摘要翻译： 描述了集成电路。 集成电路可以具有：由具有与半导体衬底的上表面平行的第一纵向方向的半导体衬底的材料形成的有源区线; 其中所述有源面积线具有至少一个形状支撑元件，所述支撑元件在平行于所述半导体衬底的上表面的第二纵向方向上延伸; 并且其中所述第二纵向方向相对于所述第一纵向方向以不等于0度并且不等于180度的角度布置。
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5.发明授权Integrated circuit with floating-gate electrodes including a transition metal and corresponding manufacturing method 有权具有包括过渡金属的浮栅电极的集成电路及相应的制造方法公开(公告)号：US08258564B2
公开(公告)日：2012-09-04
申请号：US12104750
申请日：2008-04-17
申请人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
发明人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
IPC分类号： H01L29/788
CPC分类号： H01L27/11521
摘要： An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.
摘要翻译： 描述了集成电路。 集成电路可以包括多个浮栅电极，其中浮栅电极中的至少一个具有较低宽度和上宽度，下宽度大于上宽度，并且其中至少一个 浮栅电极包括过渡金属。 还描述了集成电路的相应制造方法。
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公开(公告)号：US07785953B2
公开(公告)日：2010-08-31
申请号：US12112379
申请日：2008-04-30
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L21/31053 , H01L21/3212 , H01L29/66825 , H01L29/7881
摘要： A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into every second trench of the first plurality of trenches. Furthermore, a method for forming floating-gate electrodes on a semiconductor substrate and an integrated circuit is described.
摘要翻译： 描述了在半导体衬底的表面上形成沟槽的方法。 该方法可以包括：将第一多个沟槽蚀刻到半导体衬底的表面中; 用至少一种材料填充所述第一多个沟槽; 以及将第二多个沟槽蚀刻到所述第一多个沟槽的每个第二沟槽中。 此外，描述了在半导体衬底和集成电路上形成浮置栅电极的方法。
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公开(公告)号：US20090273017A1
公开(公告)日：2009-11-05
申请号：US12112379
申请日：2008-04-30
IPC分类号： H01L29/788 , H01L21/28 , H01L21/311
CPC分类号： H01L27/11521 , H01L21/31053 , H01L21/3212 , H01L29/66825 , H01L29/7881
摘要： A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into every second trench of the first plurality of trenches. Furthermore, a method for forming floating-gate electrodes on a semiconductor substrate and an integrated circuit is described.
摘要翻译： 描述了在半导体衬底的表面上形成沟槽的方法。 该方法可以包括：将第一多个沟槽蚀刻到半导体衬底的表面中; 用至少一种材料填充所述第一多个沟槽; 以及将第二多个沟槽蚀刻到所述第一多个沟槽的每个第二沟槽中。 此外，描述了在半导体衬底和集成电路上形成浮置栅电极的方法。
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8.发明授权Method of operating an integrated circuit for reading the logical state of a memory cell 有权操作用于读取存储器单元的逻辑状态的集成电路的方法公开(公告)号：US07602649B2
公开(公告)日：2009-10-13
申请号：US11849828
申请日：2007-09-04
申请人： Josef Willer , Detlev Richter
发明人： Josef Willer , Detlev Richter
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/26
摘要： In an embodiment of the invention, a method of operating an integrated circuit for reading the logical state of a selected one of a plurality of memory cells included within a memory cell string in the integrated circuit is provided.
摘要翻译： 在本发明的实施例中，提供了一种操作用于读取集成电路中的存储单元串中包括的多个存储单元中选定的一个的逻辑状态的集成电路的方法。
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公开(公告)号：US20090251968A1
公开(公告)日：2009-10-08
申请号：US12099522
申请日：2008-04-08
CPC分类号： H01L27/11578 , H01L27/11582
摘要： In an embodiment, an integrated circuit may include a metallically conductive structure, a base structure having a crystal orientation, the base structure being adjacent to the metallically conductive structure, and a nanostructure disposed on the base structure, the nanostructure having substantially the same crystal orientation as the base structure.
摘要翻译： 在一个实施例中，集成电路可以包括金属导电结构，具有晶体取向的基底结构，与金属导电结构相邻的基底结构，以及设置在基底结构上的纳米结构，纳米结构具有基本上相同的晶体取向 作为基础结构。
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公开(公告)号：US20090200533A1
公开(公告)日：2009-08-13
申请号：US12028513
申请日：2008-02-08
申请人： Klaus-Dieter Ufert , Josef Willer
发明人： Klaus-Dieter Ufert , Josef Willer
CPC分类号： H01L27/101 , H01L27/222 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/149 , H01L45/1625 , H01L45/1675
摘要： An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the resistive memory element.
摘要翻译： 描述了包括存储单元的集成电路和集成电路的制造方法。 存储单元包括掩埋栅极选择晶体管和耦合到掩埋栅选择晶体管的电阻存储元件。 电阻性存储元件基于电阻式存储元件的电阻率存储信息。
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