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公开(公告)号：US06842365B1
公开(公告)日：2005-01-11
申请号：US10656676
申请日：2003-09-05
CPC分类号： G11C11/1695 , G11C11/1675
摘要： A write driver uses a reference current that is reflected to a driver circuit by a voltage. The driver circuit is sized in relation to the device that provides the voltage so that the current through the driver is a predetermined multiple of the reference current. This voltage is coupled to the driver circuit through a switch. The switch is controlled so that the driver circuit only receives the voltage when the write line is to have write current through it as determined by a decoder responsive to an address. The driver is affirmatively disabled when the write line is intended to not have current passing through it. As an enhancement to overcome ground bounce due to high currents, the input to the driver can be capacitively coupled to the ground terminal that experiences such bounce. Additional enhancements provide benefits in amplitude and edge rate control.
摘要翻译： 写驱动器使用通过电压反映到驱动器电路的参考电流。 驱动器电路的尺寸相对于提供电压的装置的尺寸，使得通过驱动器的电流是参考电流的预定倍数。 该电压通过开关耦合到驱动电路。 开关被控制，使得驱动电路仅在响应于地址由解码器确定的写入线要具有写入电流时才接收电压。 当写行意图没有电流通过它时，驱动程序被肯定地禁用。 作为克服由于高电流引起的地面反弹的增强，驱动器的输入可以电容耦合到经历这种反弹的接地端子。 附加的增强功能可以提供幅度和边缘速率控制的优点。
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公开(公告)号：US06714440B2
公开(公告)日：2004-03-30
申请号：US10185888
申请日：2002-06-28
IPC分类号： G11C1100
CPC分类号： G11C11/15
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.
摘要翻译： 磁阻随机存取存储器（MRAM）具有单独的读写路径。 每个具有多个串联级的可切换电流镜接收公共参考电流。 定时电路向字和位解码器和可切换电流镜提供控制信号，以选择性地完成通过预定写字线和预定写位线的电流路径。 位线在公共端连接在一起，字线在公共端连接在一起。 通过对连接在一起的多个写入位线的共轨进行预充电，改善了写入噪声抗扰度并使电流尖峰最小化。 位线组可以通过金属选项来连接，以调整编程电流的转换时间。
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公开(公告)号：US06621729B1
公开(公告)日：2003-09-16
申请号：US10185224
申请日：2002-06-28
IPC分类号： G11C1100
CPC分类号： G11C11/14 , G11C7/062 , G11C7/067 , G11C2207/063
摘要： A sense amplifier (10) develops internally a midpoint reference current from two reference bits. The midpoint reference current is used to sense the state of a memory bit having at least two distinct resistance states (H and L) by determining whether the sense memory bit develops a larger or smaller current. The midpoint reference current is developed within a single sense amplifier. Predetermined bias voltages are developed from each of a data bit cell, a reference cell programmed to a high state and a reference cell programmed to a low state. Currents are developed from the bias voltages and summed to create the midpoint reference current. A current differential amplifier senses whether the bit input has a high or low resistive state and outputs a voltage indicative of the sensed memory state.
摘要翻译： 读出放大器（10）内部产生来自两个参考位的中点参考电流。 中点参考电流用于通过确定感测存储器位是否产生较大或更小的电流来感测具有至少两个不同电阻状态（H和L）的存储器位的状态。 在单个读出放大器内开发中点参考电流。 从数据位单元，被编程为高状态的参考单元和被编程为低状态的参考单元中的每一个产生预定的偏置电压。 电流从偏置电压开始，并相加以产生中点参考电流。 电流差分放大器感测位输入是否具有高电阻状态或低电阻状态，并且输出指示感测到的存储器状态的电压。
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14.发明授权Sense amplifier for a memory having at least two distinct resistance states 失效用于具有至少两个不同电阻状态的存储器的感测放大器公开(公告)号：US06600690B1
公开(公告)日：2003-07-29
申请号：US10184784
申请日：2002-06-28
IPC分类号： G11C702
CPC分类号： G11C11/14 , G11C7/067 , G11C7/14 , G11C2207/063
摘要： In a memory, a sensing system detects bit states using one data and two reference inputs, to sense a difference in conductance of a selected memory bit cell and a midpoint reference conductance. Reference conductance is generated as the average conductance of a memory cell in the high conductance state and a memory cell in the low conductance state. The data input is coupled to the selected memory bit cell. The two reference inputs are respectively coupled to memory cells in high and low conductance memory states. The sense amplifiers use either current biasing or voltage biasing to apply a sensing voltage within a predetermined voltage range across the bit cells. Capacitance coupled to complementary outputs of the sense amplifiers is balanced by the circuit designs. In one form, the two reference inputs are internally connected. One of several gain stages amplifies the sense amplifier output without injecting parasitic errors.
摘要翻译： 在存储器中，感测系统使用一个数据和两个参考输入来检测位状态，以感测所选存储位单元的电导差和中点参考电导。 产生参考电导作为高电导状态的存储单元的平均电导和低电导状态的存储单元。 数据输入耦合到所选择的存储器位单元。 两个参考输入分别以高和低电导存储器状态耦合到存储器单元。 读出放大器使用电流偏置或电压偏置来在位单元之间的预定电压范围内施加感测电压。 耦合到读出放大器的互补输出的电容由电路设计来平衡。 在一种形式中，两个参考输入是内部连接的。 几个增益级之一放大读出放大器输出，而不会注入寄生错误。
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公开(公告)号：US06580298B1
公开(公告)日：2003-06-17
申请号：US10186363
申请日：2002-06-28
IPC分类号： G11C706
CPC分类号： G11C7/062 , G11C11/16 , G11C2207/063
摘要： A sense amplifier having three inputs determines the state of a memory bit cell by converting a bit input voltage, a high reference voltage, and a low reference voltage to respective current values. Current differences are formed between a bit current and a high reference current, and between a low reference current and a bit current. Current mirrors (154, 158 and 170, 166) and loads (160 and 168) are used in conjunction with current steering circuitry (150, 140, 142 and 162) to form the difference of the bit current and the high reference current and also form the difference of the low reference current and the bit current. Additionally, the sense amplifier drives differential outputs (OUT and OUT13B) to reflect the difference between the two current differential quantities.
摘要翻译： 具有三个输入的读出放大器通过将位输入电压，高参考电压和低参考电压转换为相应的电流值来确定存储器位单元的状态。 在位电流和高参考电流之间以及低参考电流和位电流之间形成电流差。 电流镜（154,158和170,166）和负载（160和168）与电流控制电路（150,140,142和162）结合使用以形成比特电流和高参考电流的差异 形成低参考电流和位电流的差异。 此外，读出放大器驱动差分输出（OUT和OUT13B）以反映两个电流差分量之间的差异。
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公开(公告)号：US07206223B1
公开(公告)日：2007-04-17
申请号：US11297203
申请日：2005-12-07
IPC分类号： G11C11/00
CPC分类号： G11C11/15
摘要： A magnetoresistive random access memory (MRAM) (900) that is susceptible to a residual magnetic field is compensated during a write operation. A first magnetic field (208) is applied to a memory cell during a first time period, the first magnetic field having a first direction (y) and a first magnitude. A second magnetic field (212) is applied to the memory cell during a second time period and having a second direction (x) and a second magnitude. A third magnetic field (702) is applied to the memory cell during a third time period, wherein the third time period overlaps at least a portion of the second time period, the third magnetic field having a third direction (−y) which is approximately opposite to the first direction of the first magnetic field. Currents are selectively applied through conductors in the memory cell to apply the three magnetic fields.
摘要翻译： 在写入操作期间补偿易受残余磁场影响的磁阻随机存取存储器（MRAM）（900）。 第一磁场（208）在第一时间周期内被施加到存储单元，第一磁场具有第一方向（y）和第一大小。 第二磁场（212）在第二时间段期间被施加到存储器单元并且具有第二方向（x）和第二大小。 在第三时间段期间，第三磁场（702）被施加到存储器单元，其中第三时间周期与第二时间段的至少一部分重叠，第三磁场具有近似的第三方向（-y） 与第一磁场的第一方向相反。 通过存储单元中的导体选择性地施加电流以施加三个磁场。
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公开(公告)号：US06903964B2
公开(公告)日：2005-06-07
申请号：US10185868
申请日：2002-06-28
CPC分类号： G11C11/16
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.
摘要翻译： 磁阻随机存取存储器（MRAM）具有单独的读写路径。 这通过不需要在特定线路上的读取和写入功能之间切换来减少外围电路。 通过具有专用于读取信号或写入信号的路径，可以针对这些功能优化电压电平。 作为仅读取功能的一部分的选择晶体管可以是低电压型，因为它们不必接收写电路的相对较高的电压。 类似地，写入电压不必降低以适应低电压型晶体管。 整体存储器的大小保持有效小，同时提高性能。 存储器单元被分组，使得与组相邻耦合到公共全局位线，这减少了为降低存储器单元选择提供电容减小组方法所需的空间。
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18.发明授权公开(公告)号：US06944052B2
公开(公告)日：2005-09-13
申请号：US10304625
申请日：2002-11-26
CPC分类号： H01L27/224 , G11C11/16
摘要： In a magnetoresistive random access memory (MRAM), a magnetic tunnel junction (MTJ) (54) cell is stacked with an asymmetric tunnel device (56). This device, when used in a crosspoint MRAM array, improves the sensing of the state or resistance of the MTJ cells. Each MTJ cell has at least two ferromagnetic layers (42, 46) separated by an insulator (44). The asymmetric tunnel device (56) is electrically connected in series with the MTJ cell and is formed by at least two conductive layers (48, 52) separated by an insulator (50). The asymmetric tunnel device may be a MIM (56), MIMIM (80) or a MIIM (70). Asymmetry results from conducting electrons in a forward biased direction at a significantly greater rate than in a reversed biased direction. Materials chosen for the asymmetric tunnel device are selected to obtain an appropriate electron tunneling barrier shape to obtain the desired rectifying current/voltage characteristic.
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公开(公告)号：US07532533B2
公开(公告)日：2009-05-12
申请号：US11737506
申请日：2007-04-19
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C11/1673 , G11C11/1695 , G11C11/5692 , G11C17/02
摘要： An antifuse circuit provides on a per bit basis a signal that indicates whether an MTJ (magnetic tunnel junction) antifuse has been previously programmed to a low resistance state in response to a program voltage. A sense amplifier provides the resistance state signal. A plurality of reference magnetic tunnel junctions are coupled in parallel and to the sense amplifier, each having a resistance within a range to provide a collective resistance that can be determined by the sense amplifier to differ from each resistance state of the MTJ antifuse. A write circuit selectively provides a current sufficient to create the program voltage when the write circuit is enabled to program the antifuse magnetic tunnel junction. Upon detecting a change in resistance in the MTJ antifuse, the write circuit reduces current supplied to the antifuse. Multiple antifuses may be programmed concurrently. Gate oxide thicknesses of transistors are adjusted for optimal performance.
摘要翻译： 反熔丝电路以每比特为基础提供一个信号，该信号指示MTJ（磁性隧道结）反熔丝是否已经被预先编程为响应于编程电压的低电阻状态。 读出放大器提供电阻状态信号。 多个参考磁隧道结并联耦合到读出放大器，每个具有一个范围内的电阻，以提供可由感测放大器确定的不同于MTJ反熔丝的每个电阻状态的集合电阻。 写入电路选择性地提供足以在写入电路被编程反熔丝磁性隧道结时产生编程电压的电流。 当检测到MTJ反熔丝中的电阻变化时，写入电路减少提供给反熔丝的电流。 多个反熔丝可以同时编程。 调整晶体管的栅极氧化物厚度以获得最佳性能。
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公开(公告)号：US07224630B2
公开(公告)日：2007-05-29
申请号：US11166139
申请日：2005-06-24
IPC分类号： G11C7/02
CPC分类号： G11C17/18 , G11C11/1673 , G11C11/1695 , G11C11/5692 , G11C17/02
摘要： An antifuse circuit provides on a per bit basis a signal that indicates whether an MTJ (magnetic tunnel junction) antifuse has been previously programmed to a low resistance state in response to a program voltage. A sense amplifier provides the resistance state signal. A plurality of reference magnetic tunnel junctions are coupled in parallel and to the sense amplifier, each having a resistance within a range to provide a collective resistance that can be determined by the sense amplifier to differ from each resistance state of the MTJ antifuse. A write circuit selectively provides a current sufficient to create the program voltage when the write circuit is enabled to program the antifuse magnetic tunnel junction. Upon detecting a change in resistance in the MTJ antifuse, the write circuit reduces current supplied to the antifuse. Multiple antifuses may be programmed concurrently. Gate oxide thicknesses of transistors are adjusted for optimal performance.
摘要翻译： 反熔丝电路以每比特为基础提供一个信号，该信号指示MTJ（磁性隧道结）反熔丝是否已经被预先编程为响应于编程电压的低电阻状态。 读出放大器提供电阻状态信号。 多个参考磁隧道结并联耦合到读出放大器，每个具有在一个范围内的电阻，以提供可由感测放大器确定的不同于MTJ反熔丝的每个电阻状态的集合电阻。 写入电路选择性地提供足以在写入电路被编程反熔丝磁性隧道结时产生编程电压的电流。 当检测到MTJ反熔丝中的电阻变化时，写入电路减少提供给反熔丝的电流。 多个反熔丝可以同时编程。 调整晶体管的栅极氧化物厚度以获得最佳性能。
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