公开(公告)号：US11972786B2

公开(公告)日：2024-04-30

申请号：US17858596

申请日：2022-07-06

申请人： INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES

发明人： Kaiyou Wang ,  Yu Sheng

IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C11/18 ,  H10N50/85 ,  H10N52/00

CPC分类号： G11C11/161 ,  G11C11/18 ,  H10N50/85 ,  H10N52/00 ,  G11C11/1695

摘要： Provided are a function switchable random access memory, including: two electromagnetic portions configured to connect a current; a magnetic recording portion between the two electromagnetic portions and including a spin-orbit coupling layer and a magnetic tunnel junction; a pinning region between each of the electromagnetic portions and the magnetic recording portion; a cut-off region on a side of each of the electromagnetic portions opposite to the pinning region, the spin-orbit coupling layer is configured to generate a spin current under an action of the current; the two electromagnetic portions is configured to generate two magnetic domains with magnetization pointing in opposite directions under an action of the spin current; the magnetic tunnel junction is configured to generate a magnetic domain wall based on the two opposite magnetic domains and is configured to drive the magnetic domain wall to reciprocate under the action of the spin current.

公开(公告)号：US11688446B2

公开(公告)日：2023-06-27

申请号：US17846684

申请日：2022-06-22

申请人： SanDisk Technologies LLC

发明人： Michael Nicolas Albert Tran ,  Ward Parkinson ,  Michael Grobis ,  Nathan Franklin

IPC分类号： G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L27/24

CPC分类号： G11C11/1659 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  G11C11/1697 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L27/2481

摘要： Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.

公开(公告)号：US20190214554A1

公开(公告)日：2019-07-11

申请号：US15868367

申请日：2018-01-11

申请人： QUALCOMM Incorporated

发明人： Xia Li ,  Wei-Chuan Chen

IPC分类号： H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01F10/32

CPC分类号： H01L43/12 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  H01F10/3254 ,  H01F10/329 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

摘要： Double-patterned magneto-resistive random access memory (MRAM) for reducing magnetic tunnel junction (MTJ) pitch for increased MRAM bit cell density is disclosed. In one aspect, to fabricate MTJs in an MRAM array with reduced MTJ row pitch, a first patterning process is performed to provide separation areas in an MTJ layer between what will become rows of fabricated MTJs, which facilitates MTJs in a given row sharing a common bottom electrode. This reduces the etch depth and etching time needed to etch the individual MTJs in a subsequent step, can reduce lateral projections of sidewalls of the MTJs, thereby relaxing the pitch between adjacent MTJs, and may allow an initial MTJ hard mask layer to be reduced in height. A subsequent second patterning process is performed to fabricate individual MTJs. Additional separation areas are etched between free layers of adjacent MTJs in a given row to fabricate the individual MTJs.

公开(公告)号：US09916884B2

公开(公告)日：2018-03-13

申请号：US15115461

申请日：2014-03-07

申请人： Intel Corporation

发明人： Charles Augustine ,  Carlos Tokunaga ,  James W. Tschanz

IPC分类号： G11C11/16 ,  H03M1/12 ,  G11C13/00

CPC分类号： G11C11/1695 ,  G06F21/34 ,  G06F21/73 ,  G06F21/79 ,  G09C1/00 ,  G11C7/16 ,  G11C7/24 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0059 ,  G11C2013/0045 ,  G11C2013/005 ,  H03M1/12 ,  H03M1/124 ,  H04L9/0866

摘要： Described is a physically unclonable functional circuit comprising: a resistive memory device (e.g., an MTJ device) having at least two terminals; a transistor coupled to one of the at least two terminals of the resistive memory device; and an analog-to-digital converter (ADC) having an input coupled to the one of the at least two terminals of the resistive memory device.

公开(公告)号：US09870811B2

公开(公告)日：2018-01-16

申请号：US15185441

申请日：2016-06-17

申请人： QUALCOMM Incorporated

发明人： Peiyuan Wang ,  Jung Pill Kim ,  Jimmy Jianan Kan ,  Chando Park ,  Seung Kang

IPC分类号： G11C11/16 ,  G11C17/02

CPC分类号： G11C11/1675 ,  G11C7/20 ,  G11C11/1693 ,  G11C11/1695 ,  G11C14/0081

摘要： In a particular aspect, an apparatus includes a magnetic random access memory (MRAM) cell including a pair of cross coupled inverters including a first inverter and a second inverter. The first inverter includes a first transistor coupled to a first node and a second transistor coupled to the first node. The second inverter includes a third transistor coupled to a second node and a fourth transistor coupled to the second node. The MRAM cell includes a first magnetic tunnel junction (MTJ) element coupled to the second transistor and a second MTJ element coupled to the fourth transistor. The apparatus further includes a voltage initialization circuit coupled to the MRAM cell. The voltage initialization circuit is configured to substantially equalize voltages of the first node and the second node in response to an initialization signal.

公开(公告)号：US09705500B2

公开(公告)日：2017-07-11

申请号：US15285900

申请日：2016-10-05

申请人： International Business Machines Corporation

发明人： Anthony J. Annunziata ,  Chandrasekharan Kothandaraman ,  Philip L. Trouilloud

IPC分类号： G11C11/00 ,  H03K19/003 ,  G11C11/16

CPC分类号： H03K19/003 ,  G06F21/44 ,  G06K19/06196 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1695 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

摘要： The present invention provides integrated circuit chips having chip identification aspects. The chips include magnetic tunnel junction (MTJ) structures, and more specifically, include permanent bit strings used for chip identification and/or authentication. Systems and processes for chip identification are also disclosed herein. The MTJ element structures provided herein can have a defined resistance profile such that the intrinsic variability of the MTJ element structure is used to encode and generate a bit string that becomes a fingerprint for the chip. In some embodiments, an oxygen treatment covering all or a selected portion of an array of MTJ elements can be used to create a mask or secret key that can be used and implemented to enhance chip identification.

公开(公告)号：US20170178706A1

公开(公告)日：2017-06-22

申请号：US15453215

申请日：2017-03-08

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Hiroki NOGUCHI ,  Satoshi Takaya ,  Shinobu Fujita

IPC分类号： G11C11/16

CPC分类号： G11C11/1673 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1695 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79 ,  H01L28/00

摘要： According to one embodiment, a nonvolatile semiconductor memory includes a semiconductor substrate, a first substrate area in the semiconductor substrate, a first cell unit in the first substrate area, the first cell unit including a first memory cell and a first transistor, and the first transistor having a control terminal connected to a first word line, using the first substrate area as a channel and supplying a read current or a write current to the first memory cell, and a substrate potential setting circuit setting the first substrate area to a first substrate potential when the read current is supplied to the first memory cell, and setting the first substrate area to a second substrate potential different from the first substrate potential when the write current is supplied to the first memory cell.

公开(公告)号：US09582414B2

公开(公告)日：2017-02-28

申请号：US14988558

申请日：2016-01-05

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Ryousuke Takizawa

IPC分类号： G06F12/02 ,  G11C7/10 ,  G11C8/08 ,  G06F12/00 ,  G11C7/24 ,  G11C8/20 ,  G11C11/16 ,  G06F3/06 ,  G06F12/14

CPC分类号： G06F12/0238 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/1416 ,  G06F12/1425 ,  G06F12/1441 ,  G06F2212/1016 ,  G06F2212/202 ,  G11C7/1009 ,  G11C7/24 ,  G11C8/08 ,  G11C8/20 ,  G11C11/1695

摘要： A memory includes a cell array including memory cells storing data, and a write driver writing data to the cells. A write driver performs or does not perform writing of write data according to write mask data input along with the write data. A multiplexer selectively outputs a write protect signal or the write mask data. The write protect signal is fixed to a command prohibiting the write data from being written. The command is included in the write mask data. A write protect controller controls the multiplexer to output the write protect signal when an address of a write protect area in the cell array matches an address of the write data. The write protect controller controls the multiplexer to output the write mask data as it is when the address of the write protect area in the cell array does not match the address of the write data.

摘要翻译： 存储器包括包括存储数据的存储单元的单元阵列，以及写入驱动器向单元写入数据。 写入驱动器根据与写入数据一起输入的写入掩码数据执行或不执行写入数据的写入。 复用器选择性地输出写保护信号或写掩码数据。 写保护信号固定为禁止写入数据写入的命令。 该命令包含在写掩码数据中。 写保护控制器控制多路复用器输出写保护信号，当单元阵列中写保护区的地址与写入数据的地址匹配时。 写保护控制器控制多路复用器以当单元阵列中的写保护区域的地址与写数据的地址不匹配时输出写掩码数据。

公开(公告)号：US09495627B1

公开(公告)日：2016-11-15

申请号：US14969282

申请日：2015-12-15

申请人： International Business Machines Corporation

发明人： Anthony J. Annunziata ,  Chandrasekharan Kothandaraman ,  Philip L. Trouilloud

IPC分类号： G11C11/14 ,  G06K19/06 ,  H03K19/003

CPC分类号： H03K19/003 ,  G06F21/44 ,  G06K19/06196 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1695 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

摘要： The present invention provides integrated circuit chips having chip identification aspects. The chips include magnetic tunnel junction (MTJ) structures, and more specifically, include permanent bit strings used for chip identification and/or authentication. Systems and processes for chip identification are also disclosed herein. The MTJ element structures provided herein can have a defined resistance profile such that the intrinsic variability of the MTJ element structure is used to encode and generate a bit string that becomes a fingerprint for the chip. In some embodiments, an oxygen treatment covering all or a selected portion of an array of MTJ elements can be used to create a mask or secret key that can be used and implemented to enhance chip identification.

摘要翻译： 本发明提供了具有芯片识别方面的集成电路芯片。 芯片包括磁隧道结（MTJ）结构，更具体地说，包括用于芯片识别和/或认证的永久位串。 本文还公开了用于芯片识别的系统和过程。 本文提供的MTJ元件结构可以具有限定的电阻分布，使得MTJ元件结构的固有变化被用于编码并生成成为芯片的指纹的位串。 在一些实施例中，可以使用覆盖MTJ元件阵列的全部或选定部分的氧气处理来创建掩模或秘密密钥，其可以被使用和实现以增强芯片识别。

公开(公告)号：US20160163254A1

公开(公告)日：2016-06-09

申请号：US14957970

申请日：2015-12-03

申请人： Choong-jae Lee ,  Gwan-hyeob Koh ,  Dae-shik Kim ,  Bo-young Seo

发明人： Choong-jae Lee ,  Gwan-hyeob Koh ,  Dae-shik Kim ,  Bo-young Seo

IPC分类号： G09G3/20 ,  G06T1/60

CPC分类号： G06T1/60 ,  G06F12/00 ,  G06F12/0238 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2360/12 ,  G09G2360/18 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1695

摘要： Magnetic random access memory (MRAM)-based frame buffering apparatus are provided that may reduce a size and power consumption thereof by using a pixel self-refresh (PSR) method. The MRAM-based frame buffering apparatus includes a frame buffer memory including magnetic random access memory (MRAM). The frame buffer memory stores at least one piece of frame data. The MRAM-based frame buffering apparatus further includes a magnetic field sensor configured to detect an external magnetic field; and a frame buffer controller configured to control the storing of the at least one piece of frame data according to the intensity of the detected external magnetic field.

摘要翻译： 提供了基于磁性随机存取存储器（MRAM）的帧缓冲装置，其可以通过使用像素自刷新（PSR）方法来减小其尺寸和功耗。 基于MRAM的帧缓冲装置包括包括磁随机存取存储器（MRAM）的帧缓冲存储器。 帧缓冲存储器存储至少一个帧数据。 基于MRAM的帧缓冲装置还包括被配置为检测外部磁场的磁场传感器; 以及帧缓冲器控制器，被配置为根据所检测的外部磁场的强度来控制所述至少一帧帧数据的存储。