公开(公告)号：US20060267111A1

公开(公告)日：2006-11-30

申请号：US11436480

申请日：2006-05-18

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： A semiconductor structure and method for forming the same. The structure includes multiple fin regions disposed between first and second source/drain (S/D) regions. The structure further includes multiple front gates and back gates, each of which is sandwiched between two adjacent fin regions such that the front gates and back gates are alternating (i.e., one front gate then one back gate and then one front gate, and so on). The widths of the front gates are greater than the widths of the back gates. The capacitances of between the front gates and the S/D regions are smaller than the capacitances of between the back gates and the S/D regions. The distances between the front gates and the S/D regions are greater than the distances between the back gates and the S/D regions.

摘要翻译： 一种半导体结构及其形成方法。 该结构包括设置在第一和第二源极/漏极（S / D）区域之间的多个鳍片区域。 该结构还包括多个前门和后门，每个前门和后门夹在两个相邻鳍片区域之间，使得前门和后门交替（即，一个前门，然后一个后门，然后一个前门，等等 ）。 前门的宽度大于后门的宽度。 前门和S / D区之间的电容小于后门和S / D区之间的电容。 前门和S / D区之间的距离大于后门和S / D区之间的距离。

公开(公告)号：US20060043616A1

公开(公告)日：2006-03-02

申请号：US10711170

申请日：2004-08-30

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L31/109

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  Y10S257/90

摘要： A FinFET device and a method of lowering a gate capacitance and extrinsic resistance in a field effect transistor, wherein the method comprises forming an isolation layer comprising a BOX layer over a substrate, configuring source/drain regions above the isolation layer, forming a fin structure over the isolation layer, configuring a first gate electrode adjacent to the fin structure, disposing a gate insulator between the first gate electrode and the fin structure, positioning a second gate electrode transverse to the first gate electrode, and depositing a third gate electrode on the fin structure, the first gate electrode, and the second gate electrode, wherein the isolation layer is formed beneath the insulator, the first gate electrode, and the fin structure. The method further comprises sandwiching the second gate electrode with a dielectric material. The fin structure is formed by depositing an oxide layer over a silicon layer.

摘要翻译： FinFET器件和降低场效应晶体管中的栅极电容和非固有电阻的方法，其中所述方法包括在衬底上形成包括BOX层的隔离层，在隔离层上方构成源/漏区，形成鳍结构 在所述隔离层上方配置与所述鳍结构相邻的第一栅电极，在所述第一栅电极和所述鳍结构之间设置栅极绝缘体，将第二栅电极定位成横向于所述第一栅电极，以及将第三栅电极 鳍结构，第一栅电极和第二栅电极，其中隔离层形成在绝缘体下方，第一栅电极和鳍结构之下。 该方法还包括用电介质材料夹住第二栅电极。 翅片结构通过在硅层上沉积氧化物层而形成。

公开(公告)号：US20080083951A1

公开(公告)日：2008-04-10

申请号：US11869766

申请日：2007-10-10

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak ,  Richard Williams

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak ,  Richard Williams

IPC分类号： H01L27/12

CPC分类号： H01L29/78612 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78648

摘要： Embodiments of the invention disclose a design structure for a FET with a shallow source/drain region, a deep channel region, a gate stack and a back gate that is surrounded by dielectric. The FET structure also includes halo or pocket implants that extend through the entire depth of the channel region. Because a portion of the halo and well doping of the channel is deeper than the source/drain depth, better threshold voltage and process control is achieved. A back-gated FET structure is also provided having a first dielectric layer in this structure that runs under the shallow source/drain region between the channel region and the back gate. This first dielectric layer extends from under the source/drain regions on either side of the back gate and is in contact with a second dielectric such that the back gate is bounded on each side or isolated by dielectric.

摘要翻译： 本发明的实施例公开了具有浅电源/漏极区域，深沟道区域，栅极叠层和被电介质包围的背栅的FET的设计结构。 FET结构还包括延伸通过通道区域的整个深度的晕或凹坑植入物。 因为沟道的一部分光晕和阱掺杂比源极/漏极深度更深，所以实现了更好的阈值电压和过程控制。 还提供了后栅化FET结构，其具有在该结构中的第一介电层，其在沟道区域和后栅极之间的浅源极/漏极区域下方延伸。 该第一电介质层从背栅的两侧的源极/漏极区下方延伸并与第二电介质接触，使得后栅极在每一侧上界定或通过电介质隔离。

公开(公告)号：US20070231987A1

公开(公告)日：2007-10-04

申请号：US11761438

申请日：2007-06-12

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L27/1203 ,  H01L29/66795

摘要： A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator covering the channel portion and the channel extensions, and a gate conductor on the gate insulator. The channel extensions increase capacitance of the channel portion of the fin.

摘要翻译： 翅片型场效应晶体管（FinFET）具有鳍状物，其具有中心沟道部分，端部包括源极和漏极区域以及从鳍片的沟道部分的侧壁延伸的沟道延伸部。 该结构还包括覆盖沟道部分和沟道延伸部的栅极绝缘体以及栅极绝缘体上的栅极导体。 通道扩展增加了鳍片的通道部分的电容。

公开(公告)号：US20070122957A1

公开(公告)日：2007-05-31

申请号：US11164651

申请日：2005-11-30

申请人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Jeffrey Gambino ,  Shih-Fen Huang ,  Edward Nowak ,  Anthony Stamper

发明人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Jeffrey Gambino ,  Shih-Fen Huang ,  Edward Nowak ,  Anthony Stamper

IPC分类号： H01L21/8234 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

摘要： In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.

摘要翻译： 为了降低功耗要求，获得全电位晶体管性能并避免在高密度集成电路中对晶体管性能的功率限制，晶体管以子阈值（sub-V thth th）或 接近次级V th电压方式（通常约为0.2伏，而不是大于1.2伏特或更高的超V 2），并且针对这种操作进行了优化，特别是通过简化 的晶体管结构，因为固有沟道电阻在次级V 3工作电压方面是主要的。 这种简化包括来自栅极的源极和漏极区域的欠叠或凹陷，其避免重叠电容以部分恢复由低电压操作引起的切换速度的损失，厚度为或等于或小于500埃的超薄栅极结构 简化了与晶体管的形成连接，避免了晶体管的源极，漏极和/或栅极中的硅化或合金形成。

公开(公告)号：US20060231873A1

公开(公告)日：2006-10-19

申请号：US10907745

申请日：2005-04-14

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L29/78 ,  H01L21/84

CPC分类号： H01L29/66772 ,  H01L29/665 ,  H01L29/78645 ,  H01L29/78648

摘要： A semiconductor structure and the associated method for fabricating the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a back gate region on the semiconductor substrate, (c) a back gate dielectric region on the back gate region, (d) a semiconductor region on the back gate dielectric region comprising a channel region disposed between first and second source/drain (S/D) regions, (e) a main gate dielectric region on the semiconductor region, (f) a main gate region on the main gate dielectric region, (g) a first contact pad adjacent to the first S/D region and electrically insulated from the back gate region, and (h) a first buried dielectric region that physically and electrically isolates the first contact pad and the back gate region, and wherein the first buried dielectric region has a first thickness in the first direction at least 1.5 times a second thickness of the back gate region.

摘要翻译： 半导体结构及其制造方法。 半导体结构包括（a）半导体衬底，（b）半导体衬底上的背栅区，（c）背栅区上的背栅电介质区，（d）背栅电介质区上的半导体区，包括 设置在第一和第二源极/漏极（S / D）区域之间的沟道区域，（e）半导体区域上的主栅极电介质区域，（f）主栅极电介质区域上的主栅极区域，（g） 接触垫，其与所述第一S / D区相邻并且与所述背栅区电绝缘，以及（h）物理地和电隔离所述第一接触焊盘和所述背栅区的第一掩埋介电区，并且其中所述第一掩埋介电区 在第一方向上具有至少1.5倍于后栅极区域的第二厚度的第一厚度。

公开(公告)号：US20090057781A1

公开(公告)日：2009-03-05

申请号：US11846825

申请日：2007-08-29

申请人： Brent Anderson ,  Andres Bryant ,  Edward J. Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC分类号： H01L29/94 ,  H01L29/76

CPC分类号： H01L27/0629 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure includes active multi-gate fin-type field effect transistor (MUGFET) structures and inactive MUGFET fill structures between the active MUGFET structures. The active MUGFET structures comprise transistors that change conductivity depending upon voltages within gates of the active MUGFET structures. Conversely, the inactive MUGFET fill structures comprise passive devices that do not change conductivity irrespective of voltages within gates of the inactive MUGFET fill structures. The gates of the active MUGFET structures are parallel to the gates of the inactive MUGFET fill structures, and the fins of the active MUGFET structures are the same size as the fins of the inactive MUGFET fill structures. The active MUGFET structures have the same pitch as the gates of the inactive MUGFET fill structures. The gates of the active MUGFET structures comprise active doping agents, but the inactive MUGFET fill structures do not contain the active doping agents.

摘要翻译： 半导体结构包括有源多栅极鳍型场效应晶体管（MUGFET）结构和在活性MUGFET结构之间的无活性MUGFET填充结构。 活性MUGFET结构包括根据活性MUGFET结构的门内的电压改变导电性的晶体管。 相反，无活性的MUGFET填充结构包括不影响无活性MUGFET填充结构的门内的电压的电导率的无源器件。 活动MUGFET结构的门平行于非活性MUGFET填充结构的门，并且活动MUGFET结构的翅片与非活性MUGFET填充结构的翅片的尺寸相同。 活动的MUGFET结构具有与非活性MUGFET填充结构的门相同的间距。 活性MUGFET结构的栅极包含活性掺杂剂，但是不活泼的MUGFET填充结构不含活性掺杂剂。

公开(公告)号：US07888736B2

公开(公告)日：2011-02-15

申请号：US11846825

申请日：2007-08-29

申请人： Brent Anderson ,  Andres Bryant ,  Edward J. Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC分类号： H01L27/12

CPC分类号： H01L27/0629 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure includes active multi-gate fin-type field effect transistor (MUGFET) structures and inactive MUGFET fill structures between the active MUGFET structures. The active MUGFET structures comprise transistors that change conductivity depending upon voltages within gates of the active MUGFET structures. Conversely, the inactive MUGFET fill structures comprise passive devices that do not change conductivity irrespective of voltages within gates of the inactive MUGFET fill structures. The gates of the active MUGFET structures are parallel to the gates of the inactive MUGFET fill structures, and the fins of the active MUGFET structures are the same size as the fins of the inactive MUGFET fill structures. The active MUGFET structures have the same pitch as the gates of the inactive MUGFET fill structures. The gates of the active MUGFET structures comprise active doping agents, but the inactive MUGFET fill structures do not contain the active doping agents.

摘要翻译： 半导体结构包括有源多栅极鳍型场效应晶体管（MUGFET）结构和在活性MUGFET结构之间的无活性MUGFET填充结构。 活性MUGFET结构包括根据活性MUGFET结构的门内的电压改变导电性的晶体管。 相反，无活性的MUGFET填充结构包括不影响无活性MUGFET填充结构的门内的电压的电导率的无源器件。 活动MUGFET结构的门平行于非活性MUGFET填充结构的门，并且活动MUGFET结构的翅片与非活性MUGFET填充结构的翅片的尺寸相同。 活动的MUGFET结构具有与非活性MUGFET填充结构的门相同的间距。 活性MUGFET结构的栅极包含活性掺杂剂，但是不活泼的MUGFET填充结构不含活性掺杂剂。

公开(公告)号：US20070252282A1

公开(公告)日：2007-11-01

申请号：US11772899

申请日：2007-07-03

申请人： Brent Anderson ,  Andres Bryant ,  Jeffrey Gambino ,  Anthony Stamper

发明人： Brent Anderson ,  Andres Bryant ,  Jeffrey Gambino ,  Anthony Stamper

IPC分类号： H01L23/52

CPC分类号： H01L21/7682 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Air-gap insulated interconnection structures and methods of fabricating the structures, the methods including: forming a dielectric layer on a substrate; forming a capping layer on a top surface of the dielectric layer; forming a trench through the capping layer, the trench extending toward said substrate and into but not through, the dielectric layer; forming a sacrificial layer on opposing sidewalls of the trench; filling the trench with a electrical conductor; and removing a portion of the sacrificial layer from between the electrical conductor and the dielectric layer to form air-gaps.

摘要翻译： 气隙绝缘互连结构及其制造方法，包括：在基板上形成电介质层; 在所述电介质层的顶表面上形成覆盖层; 通过所述覆盖层形成沟槽，所述沟槽朝向所述衬底延伸并且穿过所述电介质层; 在沟槽的相对侧壁上形成牺牲层; 用电导体填充沟槽; 以及从所述电导体和所述电介质层之间移除所述牺牲层的一部分以形成气隙。

公开(公告)号：US20070278624A1

公开(公告)日：2007-12-06

申请号：US11839891

申请日：2007-08-16

申请人： Brent Anderson ,  Andres Bryant ,  Jeffrey Gambino ,  Anthony Stamper

发明人： Brent Anderson ,  Andres Bryant ,  Jeffrey Gambino ,  Anthony Stamper

IPC分类号： H01L23/60

CPC分类号： H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure. The structure includes a substrate. A first dielectric layer is on and in direct mechanical contact with the substrate. A first hard mask is on the first dielectric layer. A first and second trench is within the first dielectric layer and the first hard mask. The second trench is wider than the first trench. A first conformal liner is on sidewalls of the first and second trenches. The first conformal liner is in direct physical contact with the substrate, the first dielectric layer, and the first hard mask A first conductive material that includes copper fills the first and second trenches. A planar surface of the first conductive material is coplanar with a top surface of the first conformal liner and a top surface of the first hard mask.

摘要翻译： 一个结构。 该结构包括基底。 第一电介质层与衬底直接机械接触。 第一硬掩模在第一介电层上。 第一和第二沟槽在第一介电层和第一硬掩模内。 第二沟槽比第一沟槽宽。 第一保形衬套位于第一和第二沟槽的侧壁上。 第一共形衬垫与衬底，第一介电层和第一硬掩模直接物理接触。包括铜的第一导电材料填充第一和第二沟槽。 第一导电材料的平坦表面与第一共形衬垫的顶表面和第一硬掩模的顶表面共面。