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    Method of Forming a Fully Silicided Semiconductor Device with Independent Gate and Source/Drain Doping and Related Device
    13.
    发明申请
    Method of Forming a Fully Silicided Semiconductor Device with Independent Gate and Source/Drain Doping and Related Device 审中-公开
    形成具有独立栅极和源极/漏极掺杂和相关器件的完全硅化半导体器件的方法

    公开(公告)号：US20080265345A1

    公开(公告)日：2008-10-30

    申请号：US12135910

    申请日：2008-06-09

    申请人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

    发明人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

    IPC分类号： H01L49/00

    CPC分类号： H01L21/28097 ,  H01L29/66507 ,  H01L29/66545

    摘要： A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

    摘要翻译： 一种形成具有独立栅极和源极/漏极掺杂及相关器件的完全硅化半导体器件的方法。 示例性实施例中的至少一些是包括在衬底上形成栅极堆叠的方法（包括多晶硅层和阻挡层的栅极堆叠），以及执行离子注入到与栅极堆叠相邻的衬底的有源区域中 阻挡层基本上阻挡从多晶硅层的离子注入）。

    Method to obtain fully silicided poly gate
    14.
    发明申请
    Method to obtain fully silicided poly gate 有权
    获得完全硅化多孔的方法

    公开(公告)号：US20070037342A1

    公开(公告)日：2007-02-15

    申请号：US11201924

    申请日：2005-08-11

    申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Joe Tran

    发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Joe Tran

    IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/3205

    CPC分类号： H01L21/823425 ,  H01L21/28097 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823443 ,  H01L21/823468 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them. A protective layer 710 is placed over the capping layer 610 and the doped region 525, and a portion of the protective layer 710 and capping layer 610 that are located over the gate structures are removed to expose a top surface of the gate structures 230. A remaining portion of the protective layer 710 and capping layer 610 remains over the doped region 525. With the top surface of the gate structures 230 exposed, metal is incorporated into the gate structures to form gate electrodes 230.

    摘要翻译： 本发明提供一种制造微电子器件的方法。 在一个方面，该方法包括在位于微电子器件衬底210之上的栅极结构230上形成覆盖层610，其中栅极结构230包括侧壁间隔物515并且具有位于它们之间的掺杂区域525。 保护层710放置在覆盖层610和掺杂区域525上方，并且去除位于栅极结构上方的保护层710和覆盖层610的一部分以露出栅极结构230的顶表面。 保护层710和覆盖层610的剩余部分保留在掺杂区域525上。在栅极结构230的顶表面暴露的情况下，金属被结合到栅极结构中以形成栅电极230。

    Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device
    16.
    发明授权
    Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device 有权
    用独立的栅极和源极/漏极掺杂形成完全硅化半导体器件的方法及相关器件

    公开(公告)号：US07585738B2

    公开(公告)日：2009-09-08

    申请号：US11741540

    申请日：2007-04-27

    申请人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

    发明人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

    IPC分类号： H01L21/336 ,  H01L21/44

    CPC分类号： H01L21/28097 ,  H01L29/66507 ,  H01L29/66545

    摘要： A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

    摘要翻译： 一种形成具有独立栅极和源极/漏极掺杂及相关器件的完全硅化半导体器件的方法。 示例性实施例中的至少一些是包括在衬底上形成栅极堆叠的方法（包括多晶硅层和阻挡层的栅极堆叠），以及执行离子注入到与栅极堆叠相邻的衬底的有源区域中 阻挡层基本上阻挡从多晶硅层的离子注入）。

    Ebeam inspection for detecting gate dielectric punch through and/or incomplete silicidation or metallization events for transistors having metal gate electrodes
    18.
    发明申请
    Ebeam inspection for detecting gate dielectric punch through and/or incomplete silicidation or metallization events for transistors having metal gate electrodes 审中-公开
    用于检测栅极电介质穿透的Ebeam检查和/或用于具有金属栅电极的晶体管的不完全硅化或金属化事件

    公开(公告)号：US20080176345A1

    公开(公告)日：2008-07-24

    申请号：US11655483

    申请日：2007-01-19

    申请人： Shaofeng Yu ,  Richard L. Guldi ,  Jiong-Ping Lu ,  Freidoon Mehrad ,  Jae Hyun Park

    发明人： Shaofeng Yu ,  Richard L. Guldi ,  Jiong-Ping Lu ,  Freidoon Mehrad ,  Jae Hyun Park

    IPC分类号： H01L21/66

    CPC分类号： H01L22/14

    摘要： Gate dielectric punch through and/or incomplete silicidation or metallization events that may occur during transistor formation are identified. The events are identified just after gate electrodes are formed in order to characterize the degree of faulty transistors for process control purposes and to scrap product if sufficiently defective so that subsequent resources are not unnecessarily expended. An electron beam or ebeam is directed at locations of a workpiece whereon on or more transistors are formed. Electrons that are resultantly emitted from these locations are detected and used to develop respective gray level values (GLV's). Gate dielectric punch through and/or incomplete silicidation or metallization events are identified by finding high or low GLV's relative to neighboring areas.

    摘要翻译： 识别在晶体管形成期间可能发生的栅极电介质穿透和/或不完全的硅化或金属化事件。 在形成栅极电极之后才识别事件，以便表征用于过程控制目的的故障晶体管的程度，并且如果充分有缺陷，则废弃产品，使得后续资源不会被不必要地消耗。 电子束或ebeam被引导到其上形成有多个晶体管的工件的位置。 从这些位置发射的电子被检测并用于开发各自的灰度值（GLV's）。 通过相对于相邻区域发现高或低GLV来鉴定栅极电介质穿透和/或不完全硅化或金属化事件。

    METHOD OF FORMING A FULLY SILICIDED SEMICONDUCTOR DEVICE WITH INDEPENDENT GATE AND SOURCE/DRAIN DOPING AND RELATED DEVICE
    19.
    发明申请
    METHOD OF FORMING A FULLY SILICIDED SEMICONDUCTOR DEVICE WITH INDEPENDENT GATE AND SOURCE/DRAIN DOPING AND RELATED DEVICE 有权
    形成具有独立栅极和源/漏极掺杂的完全硅化半导体器件的方法及相关器件

    公开(公告)号：US20080265420A1

    公开(公告)日：2008-10-30

    申请号：US11741540

    申请日：2007-04-27

    申请人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

    发明人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

    IPC分类号： H01L21/3205 ,  H01L23/48

    CPC分类号： H01L21/28097 ,  H01L29/66507 ,  H01L29/66545

    摘要： A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

    摘要翻译： 一种形成具有独立栅极和源极/漏极掺杂及相关器件的完全硅化半导体器件的方法。 示例性实施例中的至少一些是包括在衬底上形成栅极堆叠的方法（包括多晶硅层和阻挡层的栅极堆叠），以及执行离子注入到与栅极堆叠相邻的衬底的有源区域中 阻挡层基本上阻挡从多晶硅层的离子注入）。

    Asymmetric static random access memory cell with dual stress liner
    20.
    发明授权
    Asymmetric static random access memory cell with dual stress liner 有权
    具有双重应力衬垫的非对称静态随机存取存储单元

    公开(公告)号：US08467233B2

    公开(公告)日：2013-06-18

    申请号：US13154225

    申请日：2011-06-06

    申请人： Shaofeng Yu ,  Wah Kit Loh

    发明人： Shaofeng Yu ,  Wah Kit Loh

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  H01L21/823807 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/7843

    摘要： A solid-state memory in which each memory cell is constructed of complementary metal-oxide-semiconductor (CMOS) inverters implemented with dual stress liner (DSL) technology. Asymmetry is incorporated into each memory cell by constructing one of the inverter transistors or the pass-gate transistor using the stress liner with opposite stress characteristics from its opposing counterpart. For example, both of the p-channel load transistors and one of the n-channel driver transistors in each memory cell may be constructed with a compressive nitride liner layer while the other driver transistor is constructed with a tensile nitride liner layer. In another implementation, one of the n-channel pass-gate transistors is constructed with a compressive nitride liner layer while the other pass-gate transistor is constructed with a tensile nitride liner layer. Improved cell stability due to the resulting asymmetric behavior is implemented in a cost-free manner.

    摘要翻译： 一种固态存储器，其中每个存储单元由用双重应力衬垫（DSL）技术实现的互补金属氧化物半导体（CMOS）反相器构成。 通过使用具有相反应力特性的应力衬垫从其相对的对应物构造逆变器晶体管或通过栅极晶体管中的一个，将不对称结合到每个存储单元中。 例如，p沟道负载晶体管和每个存储单元中的n沟道驱动晶体管中的一个可以由压缩氮化物衬垫层构成，而另一个驱动晶体管由氮化物衬垫层构成。 在另一实现中，n沟道栅极晶体管中的一个由压缩氮化物衬垫层构成，而另一个栅极晶体管由拉伸氮化物衬垫层构成。 由于产生的不对称行为而改善的细胞稳定性以无成本的方式实现。